SystemVerilog jobs in Bala Cynwyd, PA

ASIC Verification Engineer (UVM & GLS Focus)

Remote

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2d ago

Must-Have SkillsStrong end-to-end UVM expertise with hands-on experience building verification environments from scratch, including testbench architecture, agents, sequences, monitors, scoreboards, checkers, assertions, coverage models, and regression automation.Extensive Gate-Level Simulation (GLS) experience including SDF annotation, timing validation, X-propagation analysis, reset/clock synchronization issues, power-up sequence validation, and debug of post-synthesis/post-layout simulation fa

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Contract

65 - 70

FPGA Engineer

Bala Cynwyd, Pennsylvania

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Today

Overview As one of the world's largest market makers, Susquehanna was one of the first high frequency trading firms to pioneer the use of hardware-accelerated trading systems. As an FPGA Engineer at Susquehanna, you will sit at the cusp of hardware and trading and help us as we continue to build some of the industry's most cutting edge ultra-low latency trading environments. At Susquehanna, we don't believe in silos. We believe that people do their best work when they have the freedom to explor

Full-time

Design Verification Engineer

Remote

•

Yesterday

Job SummaryWe are seeking a motivated Design Verification Engineer with 13 years of experience in digital design verification and semiconductor engineering. The candidate will work with RTL design and verification teams to develop testbenches, execute simulation-based verification, debug design issues, and validate the functionality and reliability of digital designs. The ideal candidate should have hands-on knowledge of Verilog, SystemVerilog, digital logic design, and verification methodologie

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Full-time

75000 - 100,000

SoC / RTL Integration Engineer

Remote

•

Today

This is Ganesh from DELLA INFOTECH INC. We have an outstanding opening for you for the opportunity below. Please check the job description and share your updated resume, if you are interested. Job Title : SoC / RTL Integration Engineer Location : Remote Good in understanding RTL Design and Digital concepts Subsystem or SoC integration Integration 1P and 3P IP's, generating 3P fabrics, quality checks and PD handoff etc. SS integration using Verilog/system Verilog, synthesis, timing constraints,

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Contract

70 - 75

SOC/IP Integration Engineer (eInfochips Inc)

Remote or California

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Today

Position: SOC/IP Integration Engineer (eInfochips Inc) Job Description: What You'll Be Doing: Good in understanding RTL Design and Digital conceptsSubsystem or SoC integrationIntegration 1P and 3P IP's, generating 3P fabrics, quality checks and PD handoff etc.SS integration using verilog/system verilog, synthesis, timing constraints, floor-planning considerations, performance optimization, and design-quality closure including CDC, Lint, and RDC, register integration.Ensure customer satisfaction

Full-time

Senior FPGA Prototyping Engineer

Remote

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Today

K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by over $1 billion in total funding from leading investors including Altimeter Capital, ICONIQ, Kleiner Perkins, Lightspeed Venture Partners, Redpoint Ventures, and T. Rowe Price - and with over $1 billion in signed contracts across commercial and US government customers, we're mass-producing the highest-power satellite platforms ever built for missi

Full-time

USD 120,000.00 - 225,000.00 per year

Field Applications Engineer (FAE)

Remote or Maryland

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Today

Job Details: Job Description: For decades, Altera has been at the forefront of programmable logic technology. Our commitment to innovation has empowered countless customers to create groundbreaking solutions that have transformed industries. Join us in our journey to becoming the #1 FPGA company! What You Will Do As a Field Applications Engineer (FAE), your key responsibilities will be: Driving FPGA Adoption: Identify, influence, and enable the adoption of Altera FPGA-based solutions at key

Full-time

USD 134,800.00 - 195,100.00 per year

Principal FPGA Engineer

Remote or Danbury, Connecticut

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Today

Job Title: Principal FPGA Engineer Department: Product Development Reports to: Director of Hardware Engineering Office: Danbury, CT Work Location: Remote (for those in Eastern or Central time zones) Owl Cyber Defense is a leader and trusted partner in cyber security. We deliver solutions that protect and connect the world's most critical networks. Owl's product lines of cross domain, data diode, and portable media solutions provide the strongest available security checkpoints for threat preven

Full-time

USD 160,000.00 - 210,000.00 per year

ASIC Verification Engineer (UVM & GLS Focus)

Remote

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9d ago

Job Description: Must-Have Skills Strong end-to-end UVM expertise with hands-on experience building verification environments from scratch, including testbench architecture, agents, sequences, monitors, scoreboards, checkers, assertions, coverage models, and regression automation.Extensive Gate-Level Simulation (GLS) experience including SDF annotation, timing validation, X-propagation analysis, reset/clock synchronization issues, power-up sequence validation, and debug of post-synthesis/post-la

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Contract

Depends on Experience

ASIC Verification Engineer (UVM & GLS Focus)

Remote

•

9d ago

Position : ASIC Verification Engineer (UVM & GLS Focus) Location : Remote is fine Number of Positions : 7 Must-Have Skills Strong end-to-end UVM expertise with hands-on experience building verification environments from scratch, including testbench architecture, agents, sequences, monitors, scoreboards, checkers, assertions, coverage models, and regression automation.Extensive Gate-Level Simulation (GLS) experience including SDF annotation, timing validation, X-propagation analysis, reset/clock

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Contract

Depends on Experience

DFT MBIST Staff Engineer

Remote

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8d ago

Position Summary: We are looking for a highly experienced Senior MBIST Contractor to join our SoC Design-for-Test (DFT) team. The role is focused on hands-on Memory BIST implementation using Synopsys MBIST (SMS). The ideal candidate is an independent contributor who can own the complete MBIST flow from insertion through verification, simulation, pattern generation, and Silicon bring-up with minimal supervision. Responsibilities: Perform MBIST insertion for complex SoC designs using Synopsys SMS

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Contract, Third Party

90 - 100

ASIC DESIGN LEAD / SENIOR CHIP DESIGN ENGINEER

Remote

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Today

ASIC CHIP LEAD ASIC Design Lead / Senior Chip Design Engineer What Youll Do Architecture and Chip Definition Lead ASIC architecture development from high-level requirements and block diagrams. Work with system architects to define chip functionality, interfaces and performance goals. Write detailed specifications for chip components and subsystems. RTL Design and Synthesis Develop RTL designs and run synthesis with Synopsys Design Compiler. Tune RTL for power, performance and area. Design, imp

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Contract

100+

ASIC Design Lead / Senior Chip Design Engineer

Remote

•

Yesterday

Role:ASIC Design Lead / Senior Chip Design Engineer Location:REMOTE Duration: 12 months Contract Job Description What Youll Do Architecture and Chip Definition Lead ASIC architecture development from high-level requirements and block diagrams. Work with system architects to define chip functionality, interfaces and performance goals. Write detailed specifications for chip components and subsystems. RTL Design and Synthesis Develop RTL designs and run synthesis with Synopsys Design Compiler. Tun

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Contract

95 - 105

DFT MBIST Staff Engineer

Remote

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14d ago

TechAGI Solutions is looking for a highly experienced Senior MBIST Contractor to join our SoC Design-for-Test (DFT) team. The role is focused on hands-on Memory BIST implementation using Synopsys MBIST (SMS). The ideal candidate is an independent contributor who can own the complete MBIST flow from insertion through verification, simulation, pattern generation, and Silicon bring-up with minimal supervision. Responsibilities: Perform MBIST insertion for complex SoC designs using Synopsys SMS.

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Full-time

100 - 110

DFT MBIST Staff Engineer

Remote

•

Today

Contract

USD70.0/HOURLY - USD80.0/HOURLY

Principal Product Engineer - Virtual Protocols

Remote or San Jose, California

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Today

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Business Overview Deliver Emulation and Prototyping assisted verification products using virtualization (SW) technologies to accelerate and shift left SW-driven pre-silicon verification of advanced SoC designs. Job Description This Principal Product Engineer position is with the Virtual Protocols Product Engineering Team, responsible for the successful field readiness and customer dep

Full-time

USD 136,500.00 - 253,500.00 per year

SystemVerilog jobs in Bala Cynwyd, PA, USA