San Jose, California
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Today
Role: ASIC Engineering Technical Leader Location: San Jose, CA (Onsite) Start Date: Immediate Type: Contract (C2C/W2) Interview: Phone/Video We are seeking an ASIC Engineering Technical Leader with strong expertise in DesignforTest (DFT) for nextgen optical communication ASICs. Responsibilities include DFT architecture implementation, scan insertion, ATPG pattern generation, silicon debug, integration/verification of DFT fabrics, gatelevel simulations, and automation using Python/Tcl/C++.
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Full-time, Part-time, Contract, Third Party
















