Timing Closure jobs in Austin, TX

Austin, Texas

•

30+d ago

Job Description We are looking for a Physical Design Engineer with strong expertise in Place & Route (PnR), Power-Performance-Area (PPA) optimization, and timing convergence for advanced technology nodes. Key Responsibilities Drive block-level physical design implementation from netlist to GDSII. Perform floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and physical verification. Optimize designs for Power, Performance, and Area (PPA) targets. Achieve timing clo

Easy Apply

Full-time

Depends on Experience

PD Engineer, Annapurna Labs

Austin, Texas

•

Today

As a member of the Cloud-Scale Machine Learning Acceleration team you?ll be responsible for the design and optimization of Hardware in our data centers including technologies such as AWS Inferentia which is a machine learning inference product designed to deliver high performance at low cost.You?ll provide leadership in the application of new technologies to large scale deployments in a continuous effort to deliver a world-class customer experience. This is a fast-paced, intellectually challengi

Full-time

Sr. Physical Design Engineer, Amazon Leo

Austin, Texas

•

Today

Amazon Leo is an initiative to launch a constellation of Low Earth Orbit satellites that will provide low-latency, high-speed broadband connectivity to unserved and underserved communities around the world.Be part of Amazon Leo?s sub-team responsible for defining and implementing the digital chip SOCs for communications via Low Earth Orbit satellites and Amazon gateways. This is a unique opportunity to define a groundbreaking wireless solution with few legacy constraints. The team works with cus

Full-time

Staff Engineer, Physical Design

Austin, Texas

•

Today

Position Summary Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy - the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the wo

Full-time

USD 151,000.00 - 226,600.00 per year

STA - CAD Engineer

Austin, Texas

•

Today

ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world's most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you're designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger - technology that moves the world forward. Joi

Full-time

USD 126,700.00 per year

Senior Staff FPGA Engineer

Austin, Texas

•

Today

At CesiumAstro, we are developers and pioneers of out-of-the-box communication systems for satellites, UAVs, launch vehicles, and other space and airborne platforms. We take pride in our dynamic and cross-functional work environment, which allows us to learn, develop, and engage across our organization. If you are looking for hands-on, interactive, and autonomous work, CesiumAstro is the place for you. We are actively seeking passionate, collaborative, energetic, and forward-thinking individuals

Full-time

Senior Staff Engineer, Physical Design

Austin, Texas

•

Today

Full-time

USD 180,200.00 - 270,400.00 per year

Staff FPGA Verification Engineer

Austin, Texas

•

Today

Full-time

Physical Design Engineer GPU / High-Performance SoC

Remote

•

Today

Job Title: Physical Design Engineer GPU / High-Performance SoC Location: Mountain View, CA (Full Onsite) Openings: 2 Job Description We are looking for an experienced Physical Design Engineer with hands-on experience in advanced semiconductor process nodes, particularly TSMC 3nm and/or 2nm, for high-performance SoC, GPU, or similar complex chip designs. The ideal candidate will have strong end-to-end physical design experience, from netlist to GDSII, along with expertise in PPA optimization, tim

Easy Apply

Contract

$60 - $80

Senior Principal Engineer

Remote or San Jose, California

•

Today

Job Details: Job Description: Altera is looking for a Senior Principal Engineer to serve as a key technical leader responsible for defining and advancing FPGA physical synthesis, timing optimization, and implementation methodologies. This individual will bring deep expertise in EDA algorithms, optimization engines, design compilation, and performance-driven implementation technologies. The ideal candidate will have a proven track record of architecting and delivering breakthrough technologies

Full-time

USD 231,500.00 - 304,500.00 per year

Senior Staff Engineer, Physical Design (Floorplanning)

Austin, Texas

•

Today

Full-time

USD 180,200.00 - 270,400.00 per year

Asics Engineer

Remote

•

Today

Requirements please see these key words of in the project description for the profile consideration. "SCAN, ATPG, MBIST, Timing Simulations, SDF, SDC , PSV, Diagnosys , Pattern Retargeting , Pattern porting, DRCs, TetraMax, DFTMax " Experience 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requir

Full-time

VLSI Physical Design Engineer (California, Texas) - W2 Only

Austin, Texas

•

Yesterday

Hello, Hope you are doing good ! Please find the JD below and share your updated resume POSITION: VLSI Physical Design Contractor Location: San Jose, CA and Austin, TX Responsibilities We are seeking a Physical Design contractor with strong synthesis and implementation expertise to support large, timing-critical designs at advanced technology nodes. Key Responsibilities: Perform synthesis using Cadence Genus for large, timing-challenged designs Drive PPA (power, performance, area) optimization

Easy Apply

Full-time

$60 - $70

Physical Design Engineer

Remote

•

Today

Job Title: Physical Design Engineer Location: Remote We are looking for a Physical Design Engineer with hands-on experience in TSMC 3nm/2nm at SOC for cutting-edge GPU / High-Performance designs. Key Responsibilities: 1. Own Netlist-to-GDSII for high-speed, low-power SOC 2. Floorplanning, Placement, CTS, Routing, Timing closure 3. Drive PPA optimization - Power, Performance, Area for 2nm/3nm 4. Handle advanced nodes issues: IR Drop, EM, Crosstalk etc 5. Hands on experience on tools - Synopsys F

Easy Apply

Third Party, Contract

$60+

Lead ASIC DFT Staff Engineer

Remote

•

8d ago

Required Skills & Qualifications: Strong hands-on experience in ASIC DFT with end-to-end ownership.Solid understanding of DFT fundamentals, fault models, test techniques, and test coverage concepts.Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug.Hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools.Proven experience in scan insertion, ATPG setup, simulation, debug, and DRC analysis.Experience with MBIST implementation and verific

Easy Apply

Third Party, Contract

90 - 100

Memory System Designer and Place and Route Engineer

Austin, Texas

•

Today

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: We are looking for an energetic and passionate design engineer to join our Central Engineering Group and be part of a memory subsystem design team responsible for the development of large memory blocks and subsystems. Typically requires a minimum of 8

Full-time

USD 109,700.00 - 175,500.00 per year

Lead ASIC DFT Staff Engineer

Remote

•

Today

Job Description: Key Skills : "SCAN, ATPG, MBIST, Timing Simulations, SDF, SDC , PSV, Diagnosys , Pattern Retargeting , Pattern porting, DRCs, TetraMax, DFTMax " Experience: 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary: We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertio

Contract

USD70.0/HOURLY - USD80.0/HOURLY

BE CAD Physical Impl and AI Engineer

Austin, Texas

•

Today

Grow with us Principal Back-End CAD Engineer - Physical Implementation & AI, Austin, Texas This is an on-site, hybrid work schedule. This is not a remote work opportunity. About the Role As part of PEU Silicon and the Silicon CAD group, we are building the next generation of silicon development infrastructure and methodologies that power our ASIC roadmap. We are looking for a highly experienced Back-End CAD engineer who combines deep Physical Design expertise with a passion for automation, m

Full-time

Electrical Engineer, Compute Architecture

Austin, Texas

•

Today

About Neuralink: We are creating devices that enable a bi-directional interface with the brain. These devices allow us to restore movement to the paralyzed, restore sight to the blind, and revolutionize how humans interact with their digital world. Team Description: The Surgery & Robotics Hardware Team is looking for Electrical Engineers who want to advance the future of healthcare solutions with technology. At Neuralink we recognize that increasing healthcare costs, lack of access, and insuf

Full-time

USD 105,000.00 - 175,500.00 per year

Sr. Principal Software Engineer

Austin, Texas

•

Today

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence Design Systems is looking for a highly motivated hardware engineer to work with the Modus R&D engineering team in the Design-For-Test (DFT) IP business unit. As a member of the DFT R&D team, you will design and implement advanced Design-for-Test (DFT) hardware, test fabrics, and on-chip test networks used in next-generation SoCs. You will contribute to the hardware and software

Full-time

USD 196,000.00 - 364,000.00 per year

Timing Closure jobs in Austin, TX, USA