Timing Closure jobs in California

ASIC / FPGA Digital Design Engineer - (Lead or Senior)

El Segundo, California

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Today

ASIC / FPGA Digital Design Engineer - (Lead or Senior) Company: Boeing Space, Intelligence & Weapons Systems has an exciting opportunity for multiple ASIC/ FPGA Digital Design Engineers - (Lead or Senior) to join us as part of our Boeing Electronic Products team at the heart of Boeing's products to support advanced digital subsystem development in an aerospace environment in El Segundo or Huntington Beach, CA. Engineers may support ASIC, FPGA, or mixed ASIC/FPGA developments depending on progr

Full-time

USD 146,200.00 - 197,800.00 per year

Sr FPGA Design Engineer (NetSec)

California

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Today

Our Mission At Palo Alto Networks , we're united by a shared mission-to protect our digital way of life. We thrive at the intersection of innovation and impact, solving real-world problems with cutting-edge technology and bold thinking. Here, everyone has a voice, and every idea counts. If you're ready to do the most meaningful work of your career alongside people who are just as passionate as you are, you're in the right place. Who We Are In order to be the cybersecurity partner of choice, w

Full-time

USD 156,400.00 - 253,000.00 per year

ASIC / FPGA Digital Design Engineer - (Associate or Experienced)

El Segundo, California

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Today

ASIC / FPGA Digital Design Engineer - (Associate or Experienced) Company: Boeing Space, Intelligence & Weapons Systems has an exciting opportunity for multiple ASIC/ FPGA Digital Design Engineers - (Associate or Experienced) to join us as part of our Boeing Electronic Products team at the heart of Boeing's products to support advanced digital subsystem development in an aerospace environment in El Segundo or Huntington Beach, CA. Engineers may support ASIC, FPGA, or mixed ASIC/FPGA development

Full-time

USD 98,600.00 - 133,400.00 per year

Physical design Engineer

Mountain View, California

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14d ago

Position 1 Physical Design Engineer Mountain View CA (onsite - Hybrid) Mode of hiring: Fulltime permanent Customer wants someone who is having some logical design experience along with PD experience. Having some RTL2PD flow skills such as CDC/RDC/VCLP is preferred. Having some exposure of logic design is also preferred. Canddiate doesn't have to do the logic design, but needs to review the synthesis/PNR report to analyze for the timing/LoL optimization Provides services in transforming the RTL d

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Full-time

$120,000 - $140,000

Physical Design Engineer GPU / High-Performance SoC

Remote

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Today

Job Title: Physical Design Engineer GPU / High-Performance SoC Location: Mountain View, CA (Full Onsite) Openings: 2 Job Description We are looking for an experienced Physical Design Engineer with hands-on experience in advanced semiconductor process nodes, particularly TSMC 3nm and/or 2nm, for high-performance SoC, GPU, or similar complex chip designs. The ideal candidate will have strong end-to-end physical design experience, from netlist to GDSII, along with expertise in PPA optimization, tim

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Contract

$60 - $80

Physical Design Engineer Semiconductor / ASIC

Hybrid in Palo Alto, California

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Today

Physical Design Engineer Semiconductor / ASIC Location: Palo Alto, CA (100% Onsite) Openings: 5 Job Overview We are looking for an experienced Physical Design Engineer with strong hands-on expertise in end-to-end ASIC physical design and advanced semiconductor process nodes. The ideal candidate must have exposure to TSMC 2NP/3NP technology and proven experience in physical implementation, timing closure, power optimization, and physical verification. Key Responsibilities Execute the complete phy

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Contract

$70 - $90

ASIC DFT Engineer

Palo Alto, California

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Today

About Rivian Rivian is on a mission to keep the world adventurous forever. This goes for the emissions-free Electric Adventure Vehicles we build, and the curious, courageous souls we seek to attract. As a company, we constantly challenge what's possible, never simply accepting what has always been done. We reframe old problems, seek new solutions and operate comfortably in areas that are unknown. Our backgrounds are diverse, but our team shares a love of the outdoors and a desire to protect it

Full-time

Compensation information provided in the description

Elect Design and Analy Engr 3

El Segundo, California

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Today

Location: El Segundo, CA Salary: $70.00 USD Hourly - $80.00 USD Hourly Description: Our client is currently seeking a Elect Design and Analy Engr 3 Skill Code:64Y-Microelectronics Work Location: El Segundo, CA Shifts: 1st shift Time/Time Zone: 8:00 AM - 4:30 PM Job Description: - Analyzes customer and system requirements to develop basic architectural approaches and detailed specifications for various electronic products. - Develops high-level and detailed designs consistent with requirement

Contract

USD 70.00 - 80.00 per hour

ASIC/FPGA Design Verification Engineer

El Segundo, California

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Today

This posting is for a contract assignment and is not a full-time employment offer with Boeing. Candidates selected for roles will be employed as contract workers through a Boeing approved 3rd party for the duration of the specified project. Analyzes customer and system requirements to develop basic architectural approaches and detailed specifications for various electronic products. Develops high-level and detailed designs consistent with requirements and specifications. Validates designs throug

Full-time

Senior Specialist, Firmware VHDL Engineer

San Diego, California

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Today

L3Harris is dedicated to recruiting and developing high-performing talent who are passionate about what they do. Our employees are unified in a shared dedication to our customers' mission and quest for professional growth. L3Harris provides an inclusive, engaging environment designed to empower employees and promote work-life success. Fundamental to our culture is an unwavering focus on values, dedication to our communities, and commitment to excellence in everything we do. L3Harris is the Trus

Full-time

USD 106,500.00 - 197,500.00 per year

Specialist, Electrical Engineer-FPGA

San Diego, California

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Today

Full-time

USD 92,500.00 - 171,500.00 per year

Lead, Software Engineer - FPGA 1

Carlsbad, California

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Today

Full-time

USD 135,000.00 - 250,500.00 per year

Physical Design Engineer (Top-Level / Full-Chip) - AS

San Jose, California

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Yesterday

Title: Physical Design Engineer/ ASIC Implementation Engineer (Strong Top-Level / Full-Chip Physical Design and Implementation experience) Location: San Jose, CA (Onsite role) Type: FTE Permanent role Note from Hiring manager: Candidate either should have good experience on Chip level/Top level design Or if they are extremely strong in one of the other aspects of design e.g. STA (Static Timing Analysis) or Floor Planning in chip design, they can still be considered. Only in those cases where y

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Full-time

Depends on Experience

Physical Design Engineer

Palo Alto, California

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15d ago

Position: Physical Design Engineer Location : Palo Alto, CA (Full Onsite) Rate : 90-100/hr Client : HCL/Tesla Job ID : 166019 Number of Positions : 5 JD for PD: Exposure to TSMC 2NP/3NP is mustPerform endtoend physical design flow:FloorplanningPower planning (PG grid, IR)Placement & optimizationCTS (Clock Tree Synthesis)RoutingPostroute optimizationAchieve timing closure across all modes and cornersResolve DRC, LVS, ERC and signoff violationsHandle lowpower design techniques:MultiVt, Multivolta

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Contract

Depends on Experience

Physical Design Engineer

California City, California

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Today

Job Title: Physical Design Engineer Employment Type: Full-Time (FTE) Locations: San Jose, CA / San Diego, CA / Irvine, CA Experience: 12+ Years Required Technical Skills Strong hands-on experience with Cadence Innovus. End-to-end Physical Design experience from RTL to tape-out. RTL synthesis and Static Timing Analysis (STA). Timing closure, including top-level STA. Place & Route (P&R), Clock Tree Synthesis (CTS), and clock-tree optimization. Floorplanning and physical layout. Physical veri

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Full-time

Depends on Experience

Physical design engineer

San Jose, California

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Today

Position - Physical design engineer - semiconductor Location - San Jose, CA (Onsite) Experience - 5+ Years Type - W2 Contract Job Description - Physical Design - Working with Cadence Flow, InnovGenus. Working on Block Level Implementation. Experience with Place and route, Floorplanning, Synthesis and timing Closure. Working on Blocks between 1-2 million instances. Experience at 2-7nm is ideal

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Full-time, Part-time, Third Party, Contract

Physical Design Engineer – Lead

San Jose, California

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15d ago

Position: Physical Design Engineer Lead Locations: San Jose, San Diego, Irvine, CA (Onsite) What You Will Do: Drive ASIC physical design implementation from floorplanning through signoff. Perform Place & Route (PnR), Clock Tree Synthesis (CTS), timing closure, and optimization. Achieve Power, Performance, and Area (PPA) targets. Develop and validate timing constraints and perform Static Timing Analysis (STA). Execute LEC, VCLP, and EMIR signoff activities. Collaborate with cross-functional

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Full-time

Depends on Experience

Senior Principal Engineer

Remote or San Jose, California

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Today

Job Details: Job Description: Altera is looking for a Senior Principal Engineer to serve as a key technical leader responsible for defining and advancing FPGA physical synthesis, timing optimization, and implementation methodologies. This individual will bring deep expertise in EDA algorithms, optimization engines, design compilation, and performance-driven implementation technologies. The ideal candidate will have a proven track record of architecting and delivering breakthrough technologies

Full-time

USD 231,500.00 - 304,500.00 per year

Senior FPGA Engineer

San Jose, California

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Today

#WeAreIn for jobs that impact everyone's life. What if your ideas could change the way the world connects, powers up, or thinks? As a Senior FPGA Engineer in our Research & Development team, you'll have the opportunity to merge creativity with your technical expertise by shaping the future of technology, driving groundbreaking projects, and bringing new ideas to life. Are you in? Your role Key responsibilities in your new role Architect and implement FPGA solutions forprototyping platform and

Full-time

USD 91,600.00 - 126,000.00 per year

Senior FPGA Engineer

Redondo Beach, California

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Today

Senior FPGA Engineer Department: Avionics Employment Type: Full Time Location: Redondo Beach Reporting To: Farbod Kagar, Manager, Optical Communications Compensation: $145,000 - $200,000 / year Description We are seeking a highly skilled FPGA Engineer to design, implement, verify, and integrate high-performance digital logic for advanced communication and processing systems as part of Impulse's next generation of space vehicles. The ideal candidate will have strong HDL development experienc

Full-time

USD 145,000.00 - 200,000.00 per year

Timing Closure jobs in California, USA