Timing Closure jobs in California

California

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Today

Our Mission At Palo Alto Networks , we're united by a shared mission-to protect our digital way of life. We thrive at the intersection of innovation and impact, solving real-world problems with cutting-edge technology and bold thinking. Here, everyone has a voice, and every idea counts. If you're ready to do the most meaningful work of your career alongside people who are just as passionate as you are, you're in the right place. Who We Are In order to be the cybersecurity partner of choice, w

Full-time

USD 173,600.00 - 280,700.00 per year

Physical Design Engineer

Mountain View, California

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4d ago

Hi, Job Title: Physical Design Engineer (PnR / PPA / Timing Closure) Location : Mountain View, CA Responsibilities: We are looking for a Physical Design Engineer with strong expertise in Place & Route (PnR), Power-Performance-Area (PPA) optimization, and timing convergence for advanced technology nodes. Preferred Qualifications: Bachelor's or Master's degree in Electrical/Electronics Engineering.Experience in advanced nodes (7nm/5nm/3nm preferred).Strong debugging and problem-solving skills.Exp

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Full-time, Third Party

Depends on Experience

Sr. Mechanical Engineer - Closures Mechanisms

Irvine, California

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Today

About Rivian Rivian is on a mission to keep the world adventurous forever. This goes for the emissions-free Electric Adventure Vehicles we build, and the curious, courageous souls we seek to attract. As a company, we constantly challenge what's possible, never simply accepting what has always been done. We reframe old problems, seek new solutions and operate comfortably in areas that are unknown. Our backgrounds are diverse, but our team shares a love of the outdoors and a desire to protect it

Full-time

Elect Design and Analy Engr 5

El Segundo, California

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Today

Location: El Segundo, CA Salary: $110.00 USD Hourly - $112.00 USD Hourly Description: Our client is currently seeking a Elect Design and Analy Engr 5 which need active secret clearance Job Code: Elect Design and Analy Engr 5 Work Location: El Segundo, CA Shifts: 1st shift: 8:00 AM - 4:30 PM NEED ACTIVE SECRET CLEARANCE TO START WITH Job Description: The contractor will inherit FPGA top-level design and be responsible for creating and adding new functional blocks and interfaces, including in

Contract

Compensation information provided in the description

Physical Design Engineer

San Jose, California

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25d ago

Position: Physical Design Engineer Location: San Jose, CA Hybrid Duration: 12 Months VISA: H-1, USC Position Overview We are seeking an experienced Physical Design Engineer to support the implementation of high-performance semiconductor designs targeting advanced process technologies. This contract position will focus on synthesis, floorplanning, physical implementation, and performance optimization for complex, timing-sensitive designs while working closely with cross-functional engineering

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Third Party

$$70-$80 C2C

Digital Engineer (FPGA/ ASIC)

Los Angeles, California

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Today

Location: Los Angeles, CA Salary: $70.00 USD Hourly - $95.00 USD Hourly Description: Job Title: Digital Engineer (FPGA/ ASIC) Duration: 1+ year (Possible extension or Perm) Location: About the Role We are looking for you to join our team as a Principal Digital Engineer based out of Woodland Hills, CA. As a Principal Digital Engineer you will have a challenging and rewarding opportunity to be a part of our Enterprise-wide digital transformation. Using Model-based Engineering, DevSecOps and Agil

Contract

Compensation information provided in the description

ASIC/RTL Design Engineer

San Jose, California

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10d ago

Job Description: The work will expose the designer to a number of IP including ARM cores, Ethernet, DDR, DMA, PCIE, SATA and internal IPs. Successful candidates will be responsible for leading, and participating in, the design of leading edge SoC?s in advanced digital CMOS processes.Our RTL Design Engineers are expected contribute in all aspects of SoC design including: Chip definition, Architecture development and modeling, Development of micro-architectural specifications, Conversion of micro

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Third Party, Contract

Depends on Experience

Physical Design Engineer & DV Engineers

Sunnyvale, California

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20d ago

Job Title:PhysicalDesignEngineer(PD/PnR) Location Bay Area CA / Austin TX (Hybrid) Job Summary Seeking aPhysicalDesignEngineerwith strong hands-on experience in block-level and top-level Place & Route using Synopsys Fusion Compiler. The candidate will be responsible for implementation, timing closure, low-power integration, and signoff activities for complex SoCdesigns. Key Responsibilities Perform block-level and top-levelPhysicalDesignimplementation using Fusion Compiler. Drive floorplannin

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Full-time

160,000 - 170,000

Principal / Lead Engineer PCIe Gen5/Gen6 Controller, PHY & SerDes Integration

San Jose, California

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Today

Position :Principal / Lead Engineer PCIe Gen5/Gen6 Controller, PHY & SerDes Integration Location :San Jose, CA Experience :10+ years Job Summary We are seeking a highly experienced Principal/Lead Engineer to drive the architecture, development, integration, and delivery of PCIe Gen5/Gen6 subsystems for next-generation SoCs and chiplet-based products. The candidate will lead PCIe Controller, PHY and SerDes integration activities, contribute to Transaction Layer development, and work closely with

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Contract, Third Party

Depends on Experience

Senior Emulation Engineer

San Francisco, California

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2d ago

Senior Emulation EngineerExperience: 8+ Years Location: Bay Area, CA Duration: Long Term Contract Key skills: palladium or veloce or zebu, timing closure, PCIe, usb Job DescriptionWe are looking for a Senior Emulation Engineer with strong experience in hardware emulation and SoC/ASIC verification. Required Skills8+ years of experience in Hardware Emulation / SoC VerificationHands-on experience with Cadence Palladium, Siemens Veloce, or Synopsys ZeBuStrong experience in emulation bring-up, debugg

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Contract, Third Party

Depends on Experience

PD Engineer

Sunnyvale, California

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2d ago

Senior Physical Design Engineer Sunnyvale, CA, USA Fulltime Visa- G C and U S C Only We are looking for a Senior Physical Design Engineer with 814 years of experience to lead and execute RTL to GDSII implementation for low power SoCs on advanced nodes. This role demands deep expertise in Synopsys Fusion Compiler, strong scripting and automation, and a proven track record of achieving best-in-class PPA. What You will Do: Drive physical design flow: synthesis, floorplanning, placement, CTS, rout

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Full-time

Depends on Experience

Principal / Lead Design Engineer – Memory Controller (CHI-G / DFI)

San Jose, California

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2d ago

Principal / Lead Design Engineer Memory Controller (CHI-G / DFI) Were looking for an experienced Principal / Lead Design Engineer to lead RTL development and architecture updates for our Memory Controller subsystem, with strong expertise in ARM CHI-G (Coherent Hub Interface Gateway) and DDR/LPDDR/HBM PHY-facing DFI. Key Responsibilities: Modify and extend existing Memory Controller RTL for new CHI-G and DFI requirements Drive microarchitecture updates for command scheduling, arbitration, Qo

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Contract

Depends on Experience

PD Engineer

San Diego, California

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18d ago

We''re Hiring: Senior Physical Design (PD) Engineer Location: Bay Area, CA (Onsite) Experience: 8+ Years Sivaltech is looking for an experienced Senior Physical Design (PD) Engineer to join our semiconductor team. If you have expertise in advanced-node ASIC physical design and are passionate about delivering high-quality silicon, we''d love to connect with you! Key ResponsibilitiesPerform end-to-end ASIC physical design implementation from netlist to GDSII. Drive Floorplanning, Placement, Clock

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Full-time, Third Party

180,000 - 200,000

System FPGA Engineer

Remote or Utah

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Today

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > Systems Engineering General Summary: Job Description Our Mission We are dedicated to transforming the industry by reimagining silicon and developing next-generation computing platforms. By joining our team, you'll collaborate with world-class engineers to create innovative solutions that push the limits of performance, energy efficiency, and scalability. Our focus is on developing reference platforms based

Full-time

USD 146,400.00 - 219,600.00 per year

Senior Principal ASIC FPGA Engineer

Remote or Boise, Idaho

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Today

Basic Qualifications Education Requirements: Bachelor's degree in Electrical or Computer Engineering, or a related Science, Engineering or Mathematics field, plus a minimum of 10 years of relevant experience; or Master's degree plus a minimum of 8 years of relevant experience. Clearance Requirements: Ability to obtain a Department of Defense Secret security clearance is required at time of hire. Applicants selected will be subject to a U.S. Government security investigation and must meet eli

Full-time

USD 191,146.00 - 212,053.00 per year

Lead RTL/FPGA Design Engineer

Remote

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Today

About Aalyria: Aalyria is a leading technology company that supplies laser communications technology and temporospatial software-defined networking platforms to the aerospace industry. With technology acquired from Google, Aalyria is at the forefront of innovation in satellite and airborne mesh networks, as well as cislunar and deep-space communications. We are revolutionizing the orchestration and management of planetary mesh networks using any radio or optical spectrum, any orbit, and any har

Full-time

USD 170,000.00 - 195,000.00 per year

Asics Engineer

Remote

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Today

Requirements please see these key words of in the project description for the profile consideration. "SCAN, ATPG, MBIST, Timing Simulations, SDF, SDC , PSV, Diagnosys , Pattern Retargeting , Pattern porting, DRCs, TetraMax, DFTMax " Experience 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requir

Full-time

Principal Product Engineer, Synthesis

San Jose, California

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Today

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Seeking a highly motivated engineer who can drive improvement to Cadence's synthesis and place & route products from a design perspective. The position provides an excellent opportunity to work closely with the R&D team to define the roadmap of the products. Job responsibilities: Perform Product Engineering work for Genus Synthesis Solution (Genus), a logic synthesis software used for

Full-time

USD 136,500.00 - 253,500.00 per year

Timing Engineer

San Jose, California

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Today

Job Details: Job Description: About Altera At Altera , our independence as the world's largest pure-play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry-leading FPGA expertise, our singular mission is to deliver the programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets like AI, cloud, networking, and edge. As an independent company, we move faster,

Full-time

USD 118,900.00 - 172,000.00 per year

ASIC Implementation Engineer STA

San Jose, California

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Today

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: The Full Chip Static Timing Analysis (STA) Engineer is responsible for ensuring that ASIC meets its performance targets and timing requirements across all operating conditions. Key Responsibilities: Full-Chip Timing Sign-off: Own the final timing clos

Full-time

USD 143,800.00 - 230,000.00 per year

Timing Closure jobs in California, USA