Timing Closure jobs in San Francisco, CA

Palo Alto, California

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14d ago

Position: Physical Design Engineer Location : Palo Alto, CA (Full Onsite) Rate : 90-100/hr Client : HCL/Tesla Job ID : 166019 Number of Positions : 5 JD for PD: Exposure to TSMC 2NP/3NP is mustPerform endtoend physical design flow:FloorplanningPower planning (PG grid, IR)Placement & optimizationCTS (Clock Tree Synthesis)RoutingPostroute optimizationAchieve timing closure across all modes and cornersResolve DRC, LVS, ERC and signoff violationsHandle lowpower design techniques:MultiVt, Multivolta

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Contract

Depends on Experience

Physical Design Engineer Semiconductor / ASIC

Hybrid in Palo Alto, California

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Today

Physical Design Engineer Semiconductor / ASIC Location: Palo Alto, CA (100% Onsite) Openings: 5 Job Overview We are looking for an experienced Physical Design Engineer with strong hands-on expertise in end-to-end ASIC physical design and advanced semiconductor process nodes. The ideal candidate must have exposure to TSMC 2NP/3NP technology and proven experience in physical implementation, timing closure, power optimization, and physical verification. Key Responsibilities Execute the complete phy

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Contract

$70 - $90

FPGA Design Engineer

San Francisco, California

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Today

At Ouster, we build sensors and tools for engineers, roboticists, and researchers, so they can make the world safer and more efficient. We've transformed LIDAR from an analog device with thousands of components to an elegant digital device powered by one chip-scale laser array and one CMOS sensor. The result is a full range of high-resolution LIDAR sensors that deliver superior imaging at a dramatically lower price. Our advanced sensor hardware and vision algorithms are used in autonomous cars,

Full-time

Sr FPGA Design Engineer

San Francisco, California

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Today

Join the leader in entertainment innovation and help us design the future. At Dolby, science meets art, and high tech means more than computer code. As a member of the Dolby team, you'll see and hear the results of your work everywhere, from movie theaters to smartphones. We continue to revolutionize how people create, deliver, and enjoy entertainment worldwide. To do that, we need the absolute best talent. We're big enough to give you all the resources you need, and small enough so you can make

Full-time

USD 141,200.00 - 193,900.00 per year

Senior Principal Engineer

Remote or San Jose, California

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Today

Job Details: Job Description: Altera is looking for a Senior Principal Engineer to serve as a key technical leader responsible for defining and advancing FPGA physical synthesis, timing optimization, and implementation methodologies. This individual will bring deep expertise in EDA algorithms, optimization engines, design compilation, and performance-driven implementation technologies. The ideal candidate will have a proven track record of architecting and delivering breakthrough technologies

Full-time

USD 231,500.00 - 304,500.00 per year

ASIC DFT Engineer

Palo Alto, California

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Today

About Rivian Rivian is on a mission to keep the world adventurous forever. This goes for the emissions-free Electric Adventure Vehicles we build, and the curious, courageous souls we seek to attract. As a company, we constantly challenge what's possible, never simply accepting what has always been done. We reframe old problems, seek new solutions and operate comfortably in areas that are unknown. Our backgrounds are diverse, but our team shares a love of the outdoors and a desire to protect it

Full-time

Compensation information provided in the description

Physical Design Engineer GPU / High-Performance SoC

Remote

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Today

Job Title: Physical Design Engineer GPU / High-Performance SoC Location: Mountain View, CA (Full Onsite) Openings: 2 Job Description We are looking for an experienced Physical Design Engineer with hands-on experience in advanced semiconductor process nodes, particularly TSMC 3nm and/or 2nm, for high-performance SoC, GPU, or similar complex chip designs. The ideal candidate will have strong end-to-end physical design experience, from netlist to GDSII, along with expertise in PPA optimization, tim

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Contract

$60 - $80

Asics Engineer

Remote

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Today

Requirements please see these key words of in the project description for the profile consideration. "SCAN, ATPG, MBIST, Timing Simulations, SDF, SDC , PSV, Diagnosys , Pattern Retargeting , Pattern porting, DRCs, TetraMax, DFTMax " Experience 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requir

Full-time

Physical Design Engineer

Palo Alto, California

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Today

JD for PD: Exposure to TSMC 2NP/3NP is mustPerform endtoend physical design flow:FloorplanningPower planning (PG grid, IR)Placement & optimizationCTS (Clock Tree Synthesis)RoutingPostroute optimizationAchieve timing closure across all modes and cornersResolve DRC, LVS, ERC and signoff violationsHandle lowpower design techniques:MultiVt, Multivoltage (UPF)Power gating, clock gatingPerform physical verification and signoff:STA (Primetime)SI / CrosstalkIR drop & EM analysisWork on advanced nodes (7

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Contract

Depends on Experience

Staff Electrical Engineer - FPGA

San Leandro, California

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Today

About SirenOpt At SirenOpt , we are building the manufacturing intelligence layer for advanced materials. We help manufacturers visualize, understand, and control the material behavior that determines yield, performance, and safety across energy, aerospace, automotive, electronics, and semiconductor applications. We are working on this problem because advanced materials are becoming more critical and more complex, but the tools used to manufacture them have not kept pace. Manufacturers still la

Full-time

USD 180,000.00 - 220,000.00 per year

Physical Design Engineer

Remote

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Today

Job Title: Physical Design Engineer Location: Remote We are looking for a Physical Design Engineer with hands-on experience in TSMC 3nm/2nm at SOC for cutting-edge GPU / High-Performance designs. Key Responsibilities: 1. Own Netlist-to-GDSII for high-speed, low-power SOC 2. Floorplanning, Placement, CTS, Routing, Timing closure 3. Drive PPA optimization - Power, Performance, Area for 2nm/3nm 4. Handle advanced nodes issues: IR Drop, EM, Crosstalk etc 5. Hands on experience on tools - Synopsys F

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Third Party, Contract

$60+

Lead ASIC DFT Staff Engineer

Remote

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8d ago

Required Skills & Qualifications: Strong hands-on experience in ASIC DFT with end-to-end ownership.Solid understanding of DFT fundamentals, fault models, test techniques, and test coverage concepts.Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug.Hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools.Proven experience in scan insertion, ATPG setup, simulation, debug, and DRC analysis.Experience with MBIST implementation and verific

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Third Party, Contract

90 - 100

Lead ASIC DFT Staff Engineer

Remote

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Today

Job Description: Key Skills : "SCAN, ATPG, MBIST, Timing Simulations, SDF, SDC , PSV, Diagnosys , Pattern Retargeting , Pattern porting, DRCs, TetraMax, DFTMax " Experience: 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary: We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertio

Contract

USD70.0/HOURLY - USD80.0/HOURLY

Senior Staff GPU Physical Design Engineer

Remote

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Today

Job Description Title: Senior Staff GPU Physical Design Engineer Location: Austin, TX or San Jose, CA. onsite strongly preferred Need: GPU or high-performance SoC experience. Advanced node (?5nm). Full block ownership Position Summary We are seeking a Senior Staff GPU Physical Design Engineer for our client to work on the physical implementation of high-performance GPU and system-level IP, driving execution across synthesis, place-and-route, timing closure, and signoff for their advanced tech

Contract

Timing Closure jobs in San Francisco, CA, USA