UVM jobs in Oregon

ASIC Verification Engineer (UVM & GLS Focus)

Remote

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9d ago

Position : ASIC Verification Engineer (UVM & GLS Focus) Location : Remote is fine Number of Positions : 7 Must-Have Skills Strong end-to-end UVM expertise with hands-on experience building verification environments from scratch, including testbench architecture, agents, sequences, monitors, scoreboards, checkers, assertions, coverage models, and regression automation.Extensive Gate-Level Simulation (GLS) experience including SDF annotation, timing validation, X-propagation analysis, reset/clock

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Contract

Depends on Experience

ASIC Verification Engineer (UVM & GLS Focus)

Remote

•

9d ago

Job Description: Must-Have Skills Strong end-to-end UVM expertise with hands-on experience building verification environments from scratch, including testbench architecture, agents, sequences, monitors, scoreboards, checkers, assertions, coverage models, and regression automation.Extensive Gate-Level Simulation (GLS) experience including SDF annotation, timing validation, X-propagation analysis, reset/clock synchronization issues, power-up sequence validation, and debug of post-synthesis/post-la

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Contract

Depends on Experience

ASIC Verification Engineer (UVM & GLS Focus)

Remote

•

2d ago

Must-Have SkillsStrong end-to-end UVM expertise with hands-on experience building verification environments from scratch, including testbench architecture, agents, sequences, monitors, scoreboards, checkers, assertions, coverage models, and regression automation.Extensive Gate-Level Simulation (GLS) experience including SDF annotation, timing validation, X-propagation analysis, reset/clock synchronization issues, power-up sequence validation, and debug of post-synthesis/post-layout simulation fa

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Contract

65 - 70

Design Verification Engineer

Remote

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Yesterday

Job SummaryWe are seeking a motivated Design Verification Engineer with 13 years of experience in digital design verification and semiconductor engineering. The candidate will work with RTL design and verification teams to develop testbenches, execute simulation-based verification, debug design issues, and validate the functionality and reliability of digital designs. The ideal candidate should have hands-on knowledge of Verilog, SystemVerilog, digital logic design, and verification methodologie

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Full-time

75000 - 100,000

SMTS Verification Engineering

Hillsboro, Oregon

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Today

Overview Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional junior / Recent College Graduate Design Verification Engineer to join our DRAM Controller IP team in Hillsboro, Oregon. The successful candidate will participate in pre-silicon RTL Verification activities related to Rambus DRAM controller product line for controller technologies including DDR, LPDDR, HBM, and Graphics/GDDR controller technologies. This is a Full Time position, reporting to the local onsit

Full-time

USD 100,100.00 - 185,900.00 per year

Manager, Infrastructure Governance

Remote or Ohio

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Today

What Infrastructure Governance contributes to Cardinal Health Information Technology oversees the effective development, delivery, and operation of computing and information services. This function anticipates, plans, and delivers Information Technology solutions and strategies that enable operations and drive business value. Infrastructure Governance enforces Cardinal Health's risk and security policies to ensure compliance with internal and external regulations, and to maintain a secure infr

Full-time

USD 125,300.00 - 178,900.00 per year

Design Verification (DV) engineer

Remote

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2d ago

Design Verification (DV) engineerRemote USA.ContractJob SummaryExperienced Design Verification (DV) engineer for an upcoming IP verification project.Scope of Work:Development of a comprehensive verification plan based on hardware requirements.Design, integration, and maintenance of UVM-based testbench components.Development of constrained-random test cases, sequences, and assertion-based checkers.Application of AI-based verification methods and productivity tools where appropriate.Execution of v

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Contract

65 - 70

Principal Product Engineer - Virtual Protocols

Remote or San Jose, California

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Today

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Business Overview Deliver Emulation and Prototyping assisted verification products using virtualization (SW) technologies to accelerate and shift left SW-driven pre-silicon verification of advanced SoC designs. Job Description This Principal Product Engineer position is with the Virtual Protocols Product Engineering Team, responsible for the successful field readiness and customer dep

Full-time

USD 136,500.00 - 253,500.00 per year

UVM jobs in Oregon, USA