Remote
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4d ago
Remote from PST timezone Must have high speed Ethernet/packet processing/MACSec FPGA design experience. RTL Design Engineers with deep expertise in high-speed Ethernet networking domain, with exposure in Layer2/Layer3(L2/L3) packet processing. You will work closely with the customer to develop cutting-edge network security solutions on FPGA based platforms. Strong RTL architecting and design skills in Verilog/SystemVerilog with expert knowledge of networking and wireline Ethernet packet processi
Easy Apply
Contract
Depends on Experience