Austin, Texas
•
Today
Position:Design Verification Engineer (Einfochips) Job Description:Experience: 6+ Years Location: Austin TX and San Jose CA Job Description: What candidate will Be Doing: At-least6+ years of experienceinSystem Verilog HVL and C++/CAt-least 6+ year of experience inUVM.Experience in complete verification cycle which includes development of test plan, BFM/Driver/Monitor/Scoreboard component development and integration in test bench, stress/corner testing, failure debug, gate level simulations, as
Full-time








