Verification Engineer Jobs in California

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Verification Engineer - Specialized

Cynet Systems

Santa Clara, California, USA

Contract

Job Description: Pay Range: $88hr - $103hr Responsibilities: Create and implement a verification plan. Develop and execute test cases to ensure the functionality, performance, and reliability of the chip design. CollaboXX with the hardware design team to identify and resolve issues. Work in a UVM environment. Use of Assertions, and randomized and direct tests. Code coverage and debugging. Analyze and report on verification results. Experience: 10-15 years of solid experience in UVM design veri

Design Verification Engineer

BayOne Solutions

San Jose, California, USA

Contract

Job Title - Design Verification Engineer (GPU) Duration 6+ Months Location: San Jose, CA Description As a GPU Design Verification Engineer, your talents will ensure the quality at the heart of our GPU architecture. Creativity is a necessity to overcome the challenges inherent to verifying the proper operation of our low-power GPU. Versatility and broad knowledge of state-of-the-art verification techniques including the most up-to-date I UVM version will place you among the elite within our prof

Design Verification Engineer

Mirafra Inc

San Jose, California, USA

Full-time

Experience: 6 to 15+ years of experience. Job Requirements are as below: Architect block and full-chip verification environments using HVLs and constrained random techniques for SOCs with embedded CPUs and mixed signal interfaces. Requires UVM, System Verilog, SVA Develop test plans and coverage metrics from specifications and write block and chip-level tests in C,SV,UVM Debug RTL and Gate simulations and work with design engineers to verify fixes. Write diagnostics for validation of FPGA prot

Verification Engineer, Megapack Site Controls

Tesla Motors

Palo Alto, California, USA

Full-time

The Megapack Site Controls team is looking for a passionate engineer to help Tesla facilitate the world's transition to sustainable energy. Our team is responsible for dynamics modeling, algorithm design, controls development, and simulation for Tesla Energy's industrial products. Our control system is a foundational building block for power plants and microgrids based on Megapacks, Powerpacks, solar, and wind technologies. Our mission is to empower a seamless energy transition by delivering bes

Principal Verification Engineer

OSI Engineering, Inc.

San Jose, California, USA

Full-time

A leading chip and silicon IP provider is looking to hire a talented Principal Verification Engineer to join its Memory Interconnect Design team in either San Jose, CA or Morrisville, NC. This is a great opportunity to work alongside some of the industry's top engineers to help develop cutting-edge technologies that accelerate and secure data. In this full-time role, the Principal Verification Engineer will report to the Director of Design Engineering and take a key role in product development a

Physical Verification Engineer, Dojo

Tesla Motors

Palo Alto, California, USA

Full-time

Tesla's Dojo Hardware team is looking for a Physical Verification engineer to work in Palo Alto, CA. Candidate will be responsible for SoC and Block level physical verification and sign-off. Responsibilities Implement physical verification flows (DRC/LVS/ERC/ANT/DFM/PERC) in advanced technology nodesDrive SoC level physical verification closure/sign offWork closely with physical design team on RDL/Bump routing and block level physical verification closure/sign off Requirements 3-5 years of exp

Verification Engineer

Info Way Solutions

San Francisco, California, USA

Full-time

Verification Engineer Location - Bay Area, CA Type: Full Time Qualifications ME/BE in Electrical Engineering, Computer Engineering, or related field.Experience: A MINIMUM of 8-15 years in ASIC verification in the area of data center networking.Verification Skills: Expertise in Hardware Verification and Hardware Verification Methodology (e.g., System Verilog, OVM/VMM/UVM) with a strong understanding of ASIC Design and Verification flow. Experience with functional coverage, gate/timing/power simul

ASIC Verification Engineer - Hybrid

VIVA USA INC

San Jose, California, USA

Contract

Title: ASIC Verification Engineer - Hybrid Mandatory skills: UVM, UVM design verification, UVM verification, UVM environment, AISC, SOC, AISC verification, SOC verification, DV tools, DV methodologies, CPU, I/O, Cadence, Synopsys Verification tools, Synopsys, Verdi, System Verilog, IP, I/O SOC, UVM test bench development, design verification, test plan, test verification Description: Job Duties: Participate in the functional verification of a block(s) of complex ASICs and/or IP cores for an I/O

Principal Design Verification Engineer

OSI Engineering, Inc.

San Jose, California, USA

Full-time

Principal Design Verification Engineer A leading chip and silicon IP provider focused on accelerating and securing data is looking to hire an outstanding Principal Design Verification Engineer to join its Memory Interface Chip (MIC) team in San Jose, CA. This role offers the chance to work alongside top engineering talent on innovative products that push the boundaries of speed and data security. As a Principal Design Verification Engineer, you ll play a critical role in the development of MIC

Staff Integration Engineer, Verification and Validation

Rivian

Irvine, California, USA

Full-time

About Rivian Rivian is on a mission to keep the world adventurous forever. This goes for the emissions-free Electric Adventure Vehicles we build, and the curious, courageous souls we seek to attract. As a company, we constantly challenge what's possible, never simply accepting what has always been done. We reframe old problems, seek new solutions and operate comfortably in areas that are unknown. Our backgrounds are diverse, but our team shares a love of the outdoors and a desire to protect it

CPU Verification ENgineer

TalentBridge

Menlo Park, California, USA

Contract

CPU/SOCS VERIFICATION ENGINEER Location: Menlo Park, CA 94025 ( 5 Days onsite ) Duration: 12 months + extension Job Summary: As a CPU Verification Engineer, you will be a key member of the design verification team at to deliver our high-quality next generation AI integrated, cloud-native server class SoCs. You will be responsible for defining verification strategies and architecting solutions for complex verification problems. You will partner with stakeholders in adjacent domains and enable

MLA IP Design Verification Engineer , Annapurna Labs

Annapurna Labs (U.S.) Inc.

Cupertino, California, USA

Full-time

Job summary Amazon Web Services provides a highly reliable, scalable, low-cost infrastructure platform in the cloud that powers hundreds of thousands of businesses in 190 countries around the world. We are seeking an experienced Design Verification Engineers to build the next generation of our cloud server platforms. Our success depends on our world-class infrastructure; we're handling massive scale and rapid integration of emergent technologies. As a member of the Cloud-Scale Machine Learning

Design Verification Engineer (GPU)

BayOne Solutions

San Jose, California, USA

Contract

Job Title - Design Verification Engineer (GPU) Duration 9 + Month (With the possibility of extension) Location:- San Jose (Onsite) Pay Rate :- $100/hr. - 120/hr. on w2 Description As a GPU Design Verification Engineer, your talents will ensure the quality at the heart of our GPU architecture. Creativity is a necessity to overcome the challenges inherent to verifying the proper operation of our low-power GPU. Versatility and broad knowledge of state-of-the-art verification techniques including th

Senior Design Verification Engineer

PeopleNTech

Mountain View, California, USA

Contract, Third Party

Position: Senior Design Verification Engineer Location: Mountainview, California Experience: 7 to 12 years What candidate will Be Doing: Strong expertise along-with complex SoC/IP debug is mustAt-least 5+ years of experience in System Verilog HVL and C/C++.AMBA AXI bus along-with ARM or C based processorBi-frost/Processor based C and SV/UVM mix Verification. What we are looking for: A bachelor s degree in electrical or computer engineering, accompanied by a minimum of 8 years of experience in

MLA IP Design Verification Engineer , Annapurna Labs

Annapurna Labs (U.S.) Inc.

Cupertino, California, USA

Full-time

Job summary Amazon Web Services provides a highly reliable, scalable, low-cost infrastructure platform in the cloud that powers hundreds of thousands of businesses in 190 countries around the world.We are seeking an experienced Design Verification Engineers to build the next generation of our cloud server platforms. Our success depends on our world-class infrastructure; we're handling massive scale and rapid integration of emergent technologies.As a member of the Cloud-Scale Machine Learning Acc

Sr. Systems Analyst & Verification Engineer - Onsite in Costa Mesa, CA

Dataflix Inc.

Costa Mesa, California, USA

Contract, Third Party

Overview: The Sr. Systems Analyst & Verification Engineer position projects focused on the delivery of Telematics and Connectivity Services solutions. You will interact with all levels and teams in the organization. As a Sr. Systems Analysis and Verification Engineer, you are responsible for development of the verification strategy (outline test methods, test facilities and align to product requirements) as well as reporting out on test readiness, test results and product technical risks of new

Verification Engineer

Mice Groups

Sunnyvale, California, USA

Contract

Mandatory Experience: 7 + years experience in architecting and implementing Design Verification infrastructure and executing the complete verification cycleExperience in the development of UVM based verification environments from scratchExperience with Design verification of Data-center applications like Video, AI/ML, and Networking designsMinimum Qualifications B.S or M.S degree in Electrical Engineering, Computer Engineering or Computer ScienceHands-on experience in Verilog, System Verilog, C/

Mixed-Signal Design Verification Engineer

Talent Junction, LLC.

San Jose, California, USA

Contract, Third Party

Title: Mixed-Signal Design Verification Engineer Location: San Jose, CA Key Technical Skills:UVM/System Verilog, Python, Synopsys/Cadence EDA Verifications Tools, AMS Verification Required Experience/Skills: Good knowledge of System-Verilog RTL coding including state machines, adders, multipliers, combinatorial logic, etc. Good understanding of digital design for mixed signal control loops and designing Verilog / Verilog- A code to control analog circuits (e.g. bandgap, PLL, Amplifier, Filters

System IP Design Verification Engineer

West Coast Consulting LLC

California, USA

Contract

Job Description ONSITE - San Jose, CA or Austin, TX Summary We are currently looking for exceptional hardware verification engineers to join our System IP team in our Austin, TX R & D Center (SARC) and our Advanced Computing Lab (ACL) in San Jose, CA. System IP team develops proprietary coherent interconnect and memory controller IPs deployed in many high-volume products. Job Description As a Senior Staff System IP Design Verification Contractor you will contribute to the functional verificat

Verification Engineer role in Bay Area, CA/Austin, TX (Onsite)

Yochana IT Solutions

San Francisco, California, USA

Third Party, Contract

Should be good in hands-on using SV/UVM. AMBA (especially AXI is a must) Experience in updating sequence, test, running and debugging Experience in PCIE or C based is a plus