Verilog Jobs

281 - 300 of 350 Jobs

Senior ASIC Design EngineerJob Title - Senior ASIC Design Engineer

PeopleNTechCompany Name - PeopleNTech

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San Jose, California, USA

Contract, Third Party

What candidate will Be Doing: Map multi-million gate SoC designs onto prototyping platforms, creating design partitions, FPGA builds, and testbenches to simulate FPGA components.Establish prototyping systems in the lab and contribute to defining, evolving, and supporting our prototyping methodology.Option to engage in block-level RTL design or block or top-level IP integration.Collaborate with Software, Design, and Verification teams to validate the functional and performance objectives of the S

RTL EngineerJob Title - RTL Engineer

CloudiousCompany Name - Cloudious

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Santa Clara, California, USA

Contract

Title: RTL Engineer Location: Santa Clara, CA (Day-1 onsite) Duration: 6 Months Role: Integrate RISC-V Core to SoC Key Responsibilities Integrate RISC-V CPU cores into SoC designs, collaborating with cross-functional teams (DV, physical design, architecture, verification, and post-silicon validation) to ensure seamless delivery. Develop and optimize RTL (using Verilog/SystemVerilog) for core, interconnect, and memory subsystems. Evaluate and integrate third-party IP, ensuring performance, power,

RTL Engineer: Integrate RISC-V Core to SoCJob Title - RTL Engineer: Integrate RISC-V Core to SoC

Intelliswift Software IncCompany Name - Intelliswift Software Inc

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Santa Clara, California, USA

Contract

Job Title: RTL Engineer: Integrate RISC-V Core to SoC Location(s): Santa Clara, CA - Onsite Must Have skills: 5+ years of experience in RTL design, SoC integration, or related areas.Strong hands-on experience with hardware description languages (Verilog, SystemVerilog, VHDL), EDA tools, and simulators (VCS, NC, Verilator).Deep understanding of SoC design, integration, and high-performance interfaces (e.g., AXI, TileLink, PCIe, Ethernet).Proven ability to debug and optimize designs for functiona

STA EngineerJob Title - STA Engineer

Kutir IncCompany Name - Kutir Inc

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San Jose, California, USA

Contract, Third Party

Position: STA Engineer Location: Onsite San Jose CA Duration: 6+ months In Person Interview is must Job Description: Must have/Primary skills: Fullchip timing, SDC changes back to block level, Block/Full chip SDC development, Static Timing Analysis, Primetime/Tempus What You'll Be Doing: Being a member of design team who oversees fullchip SDCs and works with physical design and DFT teams to close fullchip timing in multiple timing modes. Option to also do block level RTL design or block or t

STA EngineerJob Title - STA Engineer

Cybotic Systems LLCCompany Name - Cybotic Systems LLC

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San Jose, California, USA

Contract

Position: STA Engineer Location: San Jose CA (Day-1 Onsite) Must have/Primary skills: Fullchip timing, SDC changes back to block level, Block/Full chip SDC development, Static Timing Analysis, Primetime/Tempus What You'll Be Doing: Being a member of design team who oversees fullchip SDCs and works with physical design and DFT teams to close fullchip timing in multiple timing modes.Option to also do block level RTL design or block or top-level IP integration.Helping develop efficient methodolog

SDC EngineerJob Title - SDC Engineer

PeopleNTechCompany Name - PeopleNTech

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San Jose, California, USA

Third Party, Contract

Must have/Primary skills: Full chip timing, SDC changes back to block level, Block/Full chip SDC development, Static Timing Analysis, Primetime/Tempus What You'll Be Doing: Being a member of design team who oversees full chip SDCs and works with physical design and DFT teams to close full chip timing in multiple timing modes.Option to also do block level RTL design or block or top-level IP integration.Helping develops efficient methodology to promote block level SDCs to full chip, and to bring f

Design Verification Engineer (GPU)Job Title - Design Verification Engineer (GPU)

BayOne SolutionsCompany Name - BayOne Solutions

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San Jose, California, USA

Contract

Job Title - Design Verification Engineer (GPU) Duration 9 + Month (With the possibility of extension) Location:- San Jose (Onsite) Pay Rate :- $100/hr. - 120/hr. on w2 Description As a GPU Design Verification Engineer, your talents will ensure the quality at the heart of our GPU architecture. Creativity is a necessity to overcome the challenges inherent to verifying the proper operation of our low-power GPU. Versatility and broad knowledge of state-of-the-art verification techniques including th

Senior ASIC Design EngineerJob Title - Senior ASIC Design Engineer

PeopleNTechCompany Name - PeopleNTech

•

San Jose, California, USA

Contract, Third Party

Position: Senior ASIC Design Engineer Location: San Jose, CA (Complete onsite) Experience: 8+ years (Relevant) What candidate will Be Doing: Map multi-million gate SoC designs onto prototyping platforms, creating design partitions, FPGA builds, and testbenches to simulate FPGA components. Establish prototyping systems in the lab and contribute to defining, evolving, and supporting our prototyping methodology. Option to engage in block-level RTL design or block or top-level IP integration. Colla

Senior Design Verification EngineerJob Title - Senior Design Verification Engineer

PeopleNTechCompany Name - PeopleNTech

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Mountain View, California, USA

Contract, Third Party

Position: Senior Design Verification Engineer Location: Mountainview, California Experience: 7 to 12 years What candidate will Be Doing: Strong expertise along-with complex SoC/IP debug is mustAt-least 5+ years of experience in System Verilog HVL and C/C++.AMBA AXI bus along-with ARM or C based processorBi-frost/Processor based C and SV/UVM mix Verification. What we are looking for: A bachelor s degree in electrical or computer engineering, accompanied by a minimum of 8 years of experience in

Principal Verification EngineerJob Title - Principal Verification Engineer

OSI Engineering, Inc.Company Name - OSI Engineering, Inc.

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Raleigh, North Carolina, USA

Full-time

A leading chip and silicon IP provider is looking to hire a talented Principal Verification Engineer to join its Memory Interconnect Design team in either San Jose, CA or Morrisville, NC. This is a great opportunity to work alongside some of the industry's top engineers to help develop cutting-edge technologies that accelerate and secure data. In this full-time role, the Principal Verification Engineer will report to the Director of Design Engineering and take a key role in product development a

Principal Verification EngineerJob Title - Principal Verification Engineer

OSI Engineering, Inc.Company Name - OSI Engineering, Inc.

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San Jose, California, USA

Full-time

Design Verification EngineerJob Title - Design Verification Engineer

Mirafra IncCompany Name - Mirafra Inc

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San Jose, California, USA

Full-time

Experience: 6 to 15+ years of experience. Job Requirements are as below: Architect block and full-chip verification environments using HVLs and constrained random techniques for SOCs with embedded CPUs and mixed signal interfaces. Requires UVM, System Verilog, SVA Develop test plans and coverage metrics from specifications and write block and chip-level tests in C,SV,UVM Debug RTL and Gate simulations and work with design engineers to verify fixes. Write diagnostics for validation of FPGA prot

Electrical Engineer (Circuit Design)Job Title - Electrical Engineer (Circuit Design)

Elite TechnicalCompany Name - Elite Technical

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Manassas, Virginia, USA

Contract

Our client, a leading federal defense contractor is seeking a Mid-Level Electrical Engineer with strong circuit design experience to become an integral member of the engineering team dedicated to the development of military-grade electronics the Common Weapon Launcher (CWL) system. There are currently 20 custom cards in the process of updating, as well as creating new ones. Duties and Responsibilities - Develop new and modify existing electronics in the form of PCB designs - Analyze and design

Design Verification Engineer (GPU)Job Title - Design Verification Engineer (GPU)

West Coast Consulting LLCCompany Name - West Coast Consulting LLC

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Texas, USA

Contract

Job Description Austin, TX or San Jose, CA Onsite Description: Position Requirements: Role and Responsibilities: Key responsibilities include Work with architects and designers to build verification environments and test plans Craft functional verification coverage strategy to ensure complete test suite implementation Develop assertions and checks to optimize isolation time and produce meaningful failing signatures Analyze failing tests to root cause along, working with RTL and reference modeli

ASIC Verification Engineer - DMA/PCIeJob Title - ASIC Verification Engineer - DMA/PCIe

AMD (Advanced Micro Devices)Company Name - AMD (Advanced Micro Devices)

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Santa Clara, California, USA

Full-time

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellenc

Principal Digital ASIC Design EngineerJob Title - Principal Digital ASIC Design Engineer

91140551Company Name - 91140551

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Clearfield, Utah, USA

Full-time

Job Description: We are seeking talented and motivated individuals to tackle challenging engineering problems in advanced digital IC design. As a Principal Digital ASIC Designer, you will be responsible for designing high-performance digital ASICs in advanced technologies. You will be responsible for implementing designs from RTL through synthesis. You will work in multi-disciplinary teams with opportunities to learn, grow and contribute to a variety of projects in different application areas. R

Silicon Design EngineerJob Title - Silicon Design Engineer

AdientOne LLCCompany Name - AdientOne LLC

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Massachusetts, USA

Contract

Role: Silicon Design Engineer Location: Boxborough MA 01719 | Hybrid Duration: 12+ months The candidate will be a member of the Memory I/O design team designing High Speed IO circuits and implementing DDR IPs. The focus of the activity will be centered around spice simulations and behavior modeling. The supporting team is an established group of talented Analog/Mixed-Signal integrated circuit designers. The site includes the direct supervisor, AMS manager, IP director, and majority of the AMS

Quantum Verification EngineerJob Title - Quantum Verification Engineer

ITECSCompany Name - ITECS

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Rochester, Minnesota, USA

Third Party

Job role: Quantum Verification Engineer (Contractor) Location: Rochester, MN Remote Work Possible? No BEST RATE Role & Responsibilities Verification Ownership: Take charge of the verification triage for microprocessor components, contributing to the identification of functional and performance issues pre-silicon production. Implement best practices and innovative methodologies to ensure robust and efficient verification processes. Documentation and Communication: Thoroughly document verificat

Principal Digital Design EngineerJob Title - Principal Digital Design Engineer

OSI Engineering, Inc.Company Name - OSI Engineering, Inc.

•

San Jose, California, USA

Full-time

Principal Digital Design Engineer A premier chip and silicon IP provider focused on accelerating and securing data is seeking an exceptional Principal Digital Design Engineer to join its Memory Interface Chip (MIC) team in San Jose, CA. This is an exciting opportunity to work alongside some of the industry s most innovative engineers on cutting-edge technology that drives faster and more secure data solutions. In this full-time role, the Principal Digital Design Engineer will report directly to

Principal Design Verification EngineerJob Title - Principal Design Verification Engineer

OSI Engineering, Inc.Company Name - OSI Engineering, Inc.

•

San Jose, California, USA

Full-time

Principal Design Verification Engineer A leading chip and silicon IP provider focused on accelerating and securing data is looking to hire an outstanding Principal Design Verification Engineer to join its Memory Interface Chip (MIC) team in San Jose, CA. This role offers the chance to work alongside top engineering talent on innovative products that push the boundaries of speed and data security. As a Principal Design Verification Engineer, you ll play a critical role in the development of MIC