Asic jobs in burlingame, ca

ASIC/SOC DFT Engineer (Silicon Engineering)

Palo Alto, California

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Today

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. ASIC/SOC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world's

Full-time

USD 135,000.00 - 175,000.00 per year

Sr. ASIC DFT Engineer (Silicon)

Palo Alto, California

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Today

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. SR. ASIC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world's

Full-time

USD 175,000.00 - 280,000.00 per year

ASIC DFT Staff Engineer

Remote

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Today

Job Title: ASIC DFT Staff Engineer Location: Remote Job Description: Key Skills: "SCAN, ATPG, MBIST, Timing Simulations, SDF, SDC , PSV, Diagnosys , Pattern Retargeting , Pattern porting, DRCs, TetraMax, DFTMax " Experience: 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary: We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical own

Easy Apply

Third Party, Contract

Technical Leader Network SDK QA | Saratoga, CA

Saratoga, California

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7d ago

We are seeking a hands-on Technical Leader Network SDK QA to lead the quality strategy for next-generation switching platforms. In this role, you will own SDK validation, design automated test frameworks, mentor QA engineers, and collaborate with SDK, ASIC, and Network OS teams to ensure reliable, high-performance software releases. Required Skills: 8+ years of QA/validation experience in networking SDKs, Network OS, or embedded systemsStrong knowledge of L2/L3 networking, ACLs, QoS, and multica

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Full-time

Depends on Experience

Senior ASIC RTL DESIGN Engineer

Remote or Hybrid in Boston, Massachusetts

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11d ago

12 Months + CONTRACT Starting in September SKILLS: SENIOR ASIC RTL Design Verilog High Speed Memory Interface Experience Logic synthesis & Timing constraints Forward Error Correction (FEC), Bit Rate Error (BER) calculations Integrating Soft IP from Industry Standard and Custom IP into the design Bandwidth calculation Prefer experience with some of: LPDDR5 UFS/FlashPCIe Gen4/5

Easy Apply

Contract

90 - 130

Lead ASIC DFT Engineer

Remote

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21d ago

Role: Lead ASIC DFT Engineer Location: Remote, (Onsite) Duration: Contract Year of Exp: 10+ yrs to 15 yrs. Job Description: We are seeking a highly experienced Lead ASIC DFT Engineerto architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug efforts a

Easy Apply

Third Party, Contract

110 - 120

High-Speed EDA/CAD Engineer (Analog & Mixed Signal)

Sunnyvale, California

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7d ago

Position:High-Speed EDA/CAD Engineer (Analog & Mixed Signal) Location:Sunnyvale, CA Hybrid 3 days onsite (relocation candidates is fine) Duration:24+ month contract Domain:Analog & Mixed Signal EDA/CAD Job Description: Client is seeking an EDA/CAD Engineer to support and develop SiGe and CMOS design solutions for the high-speed analog ASIC design team. The engineer will be hands-on with all phases of tool flow, including PDK installation and support, tool support and installation, layou

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Contract

$60 - $70

Senior Electrical Engineer

Hybrid in Palo Alto, California

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3d ago

Senior Electric Engineer Youll own the electrical engineering team for a breakthrough stealth-stage neurotechnology and brain-computer interface (BCI) startup building an AI-powered neural interface platform. In this role, you will own the wearable electrical architecture from schematic through production, helping bring a highly integrated next-generation device to market. The platform combines cameras, spatial audio microphones, EEG sensors, Wi-Fi/BLE connectivity, and advanced power managemen

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Full-time

225000 - 250000

Senior ASIC Verification Engineer

San Francisco, California

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Today

At Cornelis we're building the future of AI and HPC networking with an AI-first approach to silicon and software development. We're seeking engineers who are energized by working on cutting-edge ASIC design and distributed software systems, and who are motivated to push the boundaries on how AI can transform everything from chip architecture to system performance at scale. At Cornelis we're building the future of AI and HPC networking with an AI-first approach to silicon and software developmen

Full-time

Senior ASIC Emulation Engineer

Remote

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Today

K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by $450M from leading investors including Altimeter Capital, Redpoint Ventures, T. Rowe Price, Lightspeed Venture Partners, Alpine Space Ventures, and others - with an additional $500M in signed contracts across commercial and US government customers - we're mass-producing the highest-power satellite platforms ever built for missions from LEO to deep

Full-time

USD 170,000.00 - 250,000.00 per year

Senior Principal ASIC FPGA Engineer

Remote or Boise, Idaho

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Today

Basic Qualifications Education Requirements: Bachelor's degree in Electrical or Computer Engineering, or a related Science, Engineering or Mathematics field, plus a minimum of 10 years of relevant experience; or Master's degree plus a minimum of 8 years of relevant experience. Clearance Requirements: Ability to obtain a Department of Defense Secret security clearance is required at time of hire. Applicants selected will be subject to a U.S. Government security investigation and must meet eli

Full-time

USD 191,146.00 - 212,053.00 per year

Lead ASIC DFT Engineer

Remote

•

Today

We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug efforts and drive resolution of critical silicon issues. The ideal candidate will have strong hands-on expertise in DFT fundamentals

Full-time

Digital Verification Engineer

South San Francisco, California

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Today

About Neuralink: We are creating devices that enable a bi-directional interface with the brain. These devices allow us to restore movement to the paralyzed, restore sight to the blind, and revolutionize how humans interact with their digital world. Job Description & Responsibilities: We are looking for ASIC Design Verification Engineers with strong CPU, ASIC design and verification fundamentals to work in Neuralink's System-on-Chip (SoC) department under the Implant Team. This position offers

Full-time

USD 131,000.00 - 243,000.00 per year

Acoustics Engineering Project Manager, Microphone

Cupertino, California

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Today

The Apple Acoustics Engineering Project Manager (EPM) team is looking for an EPM to drive Acoustics technology and Microphone module development and qualification planning toward product deployment. In this critical, highly collaborative, and visible role, the EPM will oversee internal efforts of the microphone and audio integration teams. The EPM will also lead cross-functional coordination with a wide array of external partners within technology and hardware engineering and beyond. Descriptio

Full-time

PMIC Engineering Program Manager

Sunnyvale, California

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Today

Apple's Power Management solutions enable the exceptional performance and battery life in every Apple product from iPhone to Mac to Watch. We're seeking a Silicon Program Manager to drive PMIC development from architecture through mass production, combining program leadership with deep technical engagement. Description In this individual contributor role, you'll own full silicon lifecycles for custom Power Management ICs and analog IP integrated into Apple SoCs in advanced process nodes. You'l

Full-time

Sr Software Engineer, Infrastructure Services (SONiC)

San Francisco, California

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Today

Do you want to help build some of the largest and most consequential enterprise and customer technology systems in the world? Join Apple's Information Systems and Technology (IS&T) organization. IS&T is the engine behind everything Apple does for customers and for the people who build for them. It's Apple's central nervous system. Supporting 2.5 billion active Apple devices, processing billions of secure transactions, and keeping the technology that defines modern life running flawlessly, IS&T

Full-time

Sr. Product Engineer

Santa Clara, California

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Today

Description Primary responsibility is to bring a new product from tapeout to mass production. Candidate designs a characterization/testing plan and works with R&D teams and manufacturing engineers on technical issues, resolving these issues to meet performance requirements on product requirement documents. For existing products, the senior product engineer will maintain and sustain technical support and actively participate in yield improvements. Description: Owner of assigned productsParticip

Full-time

USD 110,600.00 - 140,000.00 per year

Electrical Engineer

Sunnyvale, California

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Today

Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. This architecture allows Cerebras to deliver industry-leading training and inference speeds; over 10 times faster than GPU-based hyperscale cloud inference services. This order of magnitude increase in speed is transforming the user experience of AI applications, unlocking real-time iteration and increasing intelligence via additional agentic computation. Cerebras works with the leading model labs, global enterprise

Full-time

USD 150,000.00 - 260,000.00 per year

DFT Engineer

Santa Clara, California

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Today

Benefits: Day-1 Onsite Competitive salary Opportunity for advancement DFT Engineer (Design for Test) Location: Santa Clara, CA (Onsite) Employment Type: Long-Term Contract Interview Process: Virtual Interviews Compensation: Based on Experience (DOE) Engagement: ANY Preference: Local candidates or those able to work onsite We are seeking an experienced DFT Engineer to join a high-performing ASIC/SoC engineering team. In this role, you will be responsible for designing and implementing De

Full-time

Compensation information provided in the description

Principal DFT Engineer (Silicon Engineering)

Palo Alto, California

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Today

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. PRINCIPAL DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world'

Full-time

USD 220,000.00 - 355,000.00 per year

Asic jobs in Burlingame, CA, USA