Asic jobs in dc | Dice.com

ASIC Verification Engineer (UVM & GLS Focus)

Remote

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9d ago

Position : ASIC Verification Engineer (UVM & GLS Focus) Location : Remote is fine Number of Positions : 7 Must-Have Skills Strong end-to-end UVM expertise with hands-on experience building verification environments from scratch, including testbench architecture, agents, sequences, monitors, scoreboards, checkers, assertions, coverage models, and regression automation.Extensive Gate-Level Simulation (GLS) experience including SDF annotation, timing validation, X-propagation analysis, reset/clock

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Contract

Depends on Experience

Lead ASIC DFT Staff Engineer

Remote

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Today

Job Description: Key Skills : "SCAN, ATPG, MBIST, Timing Simulations, SDF, SDC , PSV, Diagnosys , Pattern Retargeting , Pattern porting, DRCs, TetraMax, DFTMax " Experience: 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary: We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertio

Contract

USD70.0/HOURLY - USD80.0/HOURLY

ASIC DESIGN LEAD / SENIOR CHIP DESIGN ENGINEER

Remote

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Today

ASIC CHIP LEAD ASIC Design Lead / Senior Chip Design Engineer What Youll Do Architecture and Chip Definition Lead ASIC architecture development from high-level requirements and block diagrams. Work with system architects to define chip functionality, interfaces and performance goals. Write detailed specifications for chip components and subsystems. RTL Design and Synthesis Develop RTL designs and run synthesis with Synopsys Design Compiler. Tune RTL for power, performance and area. Design, imp

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Contract

100+

ASIC Design Lead / Senior Chip Design Engineer

Remote

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Yesterday

Role:ASIC Design Lead / Senior Chip Design Engineer Location:REMOTE Duration: 12 months Contract Job Description What Youll Do Architecture and Chip Definition Lead ASIC architecture development from high-level requirements and block diagrams. Work with system architects to define chip functionality, interfaces and performance goals. Write detailed specifications for chip components and subsystems. RTL Design and Synthesis Develop RTL designs and run synthesis with Synopsys Design Compiler. Tun

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Contract

95 - 105

ASIC Verification Engineer (UVM & GLS Focus)

Remote

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2d ago

Must-Have SkillsStrong end-to-end UVM expertise with hands-on experience building verification environments from scratch, including testbench architecture, agents, sequences, monitors, scoreboards, checkers, assertions, coverage models, and regression automation.Extensive Gate-Level Simulation (GLS) experience including SDF annotation, timing validation, X-propagation analysis, reset/clock synchronization issues, power-up sequence validation, and debug of post-synthesis/post-layout simulation fa

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Contract

65 - 70

Lead ASIC DFT Staff Engineer

Remote

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8d ago

Required Skills & Qualifications: Strong hands-on experience in ASIC DFT with end-to-end ownership.Solid understanding of DFT fundamentals, fault models, test techniques, and test coverage concepts.Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug.Hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools.Proven experience in scan insertion, ATPG setup, simulation, debug, and DRC analysis.Experience with MBIST implementation and verific

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Third Party, Contract

90 - 100

ASIC Verification Engineer (UVM & GLS Focus)

Remote

•

9d ago

Job Description: Must-Have Skills Strong end-to-end UVM expertise with hands-on experience building verification environments from scratch, including testbench architecture, agents, sequences, monitors, scoreboards, checkers, assertions, coverage models, and regression automation.Extensive Gate-Level Simulation (GLS) experience including SDF annotation, timing validation, X-propagation analysis, reset/clock synchronization issues, power-up sequence validation, and debug of post-synthesis/post-la

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Contract

Depends on Experience

Principal Engineer - FPGA/ASIC Design

Washington, District of Columbia

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Today

Job Description Job Title: Principal Engineer - FPGA/ASIC Design Working Pattern: Hybrid (3 office days a week) Working location: Reston, VA Rolls-Royce is looking for a Principal Engineer - FPGA/ASIC Design (Field Programmable Gate Arrays / Application Specific Integrated Circuit) Design Specialist to join our growing team. This is an exciting opportunity to work on flagship Rolls-Royce programs and play a vital role in solving some of the most complex and interesting technological challen

Full-time

USD 152,033.00 - 247,054.00 per year

ASIC FPGA Engineer

Remote or Boise, Idaho

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Today

Basic Qualifications Education Requirements: Bachelor's degree in Electrical or Computer Engineering, or a related Science, Engineering or Mathematics field, plus a minimum of 2 years of relevant experience; or Master's degree, plus 6 months of relevant experience. Clearance Requirements: Ability to obtain a Department of Defense Secret security clearance is required at time of hire. Applicants selected will be subject to a U.S. Government security investigation and must meet eligibility req

Full-time

USD 103,585.00 - 110,000.00 per year

Digital Hardware Engineer

Washington, District of Columbia

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Today

Overview i3 has an exciting opportunity for a Digital Hardware Engineer to support the Naval Research Laboratory, Tactical Electronic Warfare Division. The TEWD's mission is to protect the warfighter from emerging threats by advancing electronic warfare (EW) through analysis and RDT&E of current and future technologies. Pay Range $115,000 - 189,000 The pay range for this position is a general guideline only and not a guarantee of compensation or salary. Additional factors considered in extendi

Full-time

USD 115,000.00 - 189,000.00 per year

Principal Hardware Design Engineer

Laurel, Maryland

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Today

About Leidos Leidos is a FORTUNE 500 company bringing a mix of innovative technology and sector expertise to customers in the national security, engineering, and health industries. We deliver innovative solutions through the efforts of our diverse and talented people who are dedicated to our customers' success. Guided by our Mission, Vision, and Values, Leidos empowers its teams, contributes to its communities, and operates sustainably-always with a commitment to doing the right thing for our

Full-time

USD 131,300.00 - 237,350.00 per year

Senior Hardware Engineer

Reston, Virginia

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Today

Seekr is an AI-focused firm delivering advanced, mission-critical agentic edge solutions for defense and national-security customers. Our AI platform powers intelligence-surveillance-reconnaissance (ISR) and command-and-control (C2) solutions that run on cloud, on-premises, and edge environments, supporting both classified and unclassified operations. Position Overview The Senior Hardware Engineer will join the Director of Mission Solutions' multidisciplinary team of architects, ML engineers,

Full-time

USD 160,000.00 - 230,000.00 per year

DFT (Design For Test) Lead - Remote Role

Remote

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Today

Role: ASIC DFT (Design for Test) LeadLocation: RemoteDuration: 12+ months (possibly extending longer based on project timelines)Candidate Responsibilities:Responsible for implementing the Hardware Design-for-Test (DFT) features - scan, mbist, BISR, boundary scan, setting up/debugging DFT simulations and supporting post-silicon testing/debugResponsible for development of innovative DFT IP in collaboration with the multi-functional teams, and play a key role in full chip design integration with t

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Contract

Depends on Experience

DFT (Design for Test) Lead

Remote

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21d ago

Job Title: DFT (Design for Test) Lead Location: (Remote) Shift: 9am 5pm PST Duration: 12+ Months Contract Role on W2 Job Responsibilities:Responsible for implementing the Hardware Design-for-Test (DFT) features - scan, mbist, BISR, boundary scan, setting up/debugging DFT simulations and supporting post-silicon testing/debugResponsible for development of innovative DFT IP in collaboration with the multi-functional teams, and play a key role in full chip design integration with the testability f

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Contract

75 - 80

Sr. Field Application Engineer

Remote or Minnesota

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Today

Monolithic Power Systems, Inc. (MPS) is one of the fastest growing companies in the Semiconductor industry. We are worldwide technical leaders in Integrated Power Semiconductors and Systems Power delivery architectures. At MPS, we cultivate creativity, are passionate about sustainability, and are committed to providing leading-edge products and innovation to our customers. Our portfolio of technology helps power our world come join our team and see how YOU can make a difference. Job Description

Full-time

Lead AI Engineer with Machine Learning

Remote

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Today

We are seeking a Lead AI Engineer to join a cutting-edge team building computers designed specifically for AI. Our customer brings together experts in computer architecture, ASIC design, advanced systems, and neural network compilers to build the next generation of computing. The team is actively working on compilers, neural networks, LLMs, and CNNs, and is looking for an experienced engineer to take on a Key Developer role within the ML & AI team. Responsibilities Design, implement, and iterate

Full-time

Lead ASIC DFT Engineer

Remote

•

Today

We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug efforts and drive resolution of critical silicon issues. The ideal candidate will have strong hands-on expertise in DFT fundamentals

Full-time

Principal SOC Architect, AI Accelerators (Multiple Locations

Remote or San Diego, California

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Today

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: Qualcomm is looking for an experienced SoC architect to work on the next generation AI products in the datacenter. We are looking for a data center engineer whose expertise spans security, RAS and/or virtualization. The selected candidate will help define the architecture and drive requirements from card/server level to a full rack. Responsibilities: Understand trends in

Full-time

USD 200,000.00 - 300,000.00 per year

Senior Principal Engineer

Remote or San Jose, California

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Today

Job Details: Job Description: Altera is looking for a Senior Principal Engineer to serve as a key technical leader responsible for defining and advancing FPGA physical synthesis, timing optimization, and implementation methodologies. This individual will bring deep expertise in EDA algorithms, optimization engines, design compilation, and performance-driven implementation technologies. The ideal candidate will have a proven track record of architecting and delivering breakthrough technologies

Full-time

USD 231,500.00 - 304,500.00 per year

Principal Engineer, Hardware Design - Networking

Remote

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Today

Req ID: 140081 Region: Americas Country: USA State/Province: New Hampshire City: Remote Employee US Summary Celestica is seeking a Principal Hardware Systems Architect for Networking Platforms to provide senior technical leadership for the architecture and development of next-generation AI, cloud, and high-performance data center networking platforms. This role will lead networking-platform architecture spanning high-performance Ethernet and InfiniBand-class fabrics, switching systems, NICs/DPU

Full-time

Asic jobs in Washington, DC, USA