design verification engineer Jobs

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Silicon Design Verification Engineer IIIJob Title - Silicon Design Verification Engineer III

Ascendion Inc.Company Name - Ascendion Inc.

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Burlingame, California, USA

Full-time

About Ascendion Ascendion is a full-service digital engineering solutions company. We make and manage software platforms and products that power growth and deliver captivating experiences to consumers and employees. Our engineering, cloud, data, experience design, and talent solution capabilities accelerate transformation and impact for enterprise clients. Headquartered in New Jersey, our workforce of 11,000+ Ascenders delivers solutions from around the globe. Ascendion is built differently to e

Design Verification EngineerJob Title - Design Verification Engineer

Mirafra IncCompany Name - Mirafra Inc

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San Jose, California, USA

Full-time

Experience: 6 to 15+ years of experience. Job Requirements are as below: Architect block and full-chip verification environments using HVLs and constrained random techniques for SOCs with embedded CPUs and mixed signal interfaces. Requires UVM, System Verilog, SVA Develop test plans and coverage metrics from specifications and write block and chip-level tests in C,SV,UVM Debug RTL and Gate simulations and work with design engineers to verify fixes. Write diagnostics for validation of FPGA prot

Design Verification EngineerJob Title - Design Verification Engineer

SivaltechCompany Name - Sivaltech

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Santa Clara, California, USA

Contract, Third Party

Job Title: Design Verification Engineer (DV) Company: Sivaltech Location: Santa Clara, CA Job Type: Full-time About Sivaltech: Sivaltech is a leading technology company driving innovation in the industry. We're seeking an experienced Design Verification Engineer to join our team in Santa Clara, CA. Job Description: As a Design Verification Engineer, you'll develop and execute verification plans for complex digital designs, focusing on Ethernet PHY or PCS. You'll work closely with cross-functiona

Senior Design Verification Engineer-12+Yrs Candidate neededJob Title - Senior Design Verification Engineer-12+Yrs Candidate needed

SivaltechCompany Name - Sivaltech

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San Diego, California, USA

Contract, Third Party

Job Title: Senior Design Verification Engineer Company: Sivaltech Location: San Diego, CA Job Type: Full-time About Sivaltech: Sivaltech is a leading technology company driving innovation and excellence in the industry. We're seeking an experienced Senior Design Verification Engineer to join our team in San Diego, CA. Job Description: As a Senior Design Verification Engineer, you'll develop and execute verification plans for complex digital designs, working closely with cross-functional teams to

GLS Design Verification EngineerJob Title - GLS Design Verification Engineer

VDart, Inc.Company Name - VDart, Inc.

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Toronto, Ontario, Canada

Contract, Third Party

Job Title: GLS Design Verification Engineer Location: Canada Remote Duration / Term: 6+ months Contract Job Description: Good DV Skill with major GLS work experience.Expertise in testbench updates for GLSExpertise in Scripting languages perl or pythonExperience with Make, Yaml & Json file systems.Experience with 0 delay simulations and post layout simulations with SDF back annotations (Best/Typical/Worst Case analysis).Good understanding of RTL synthesis, Static Timing Analysis & LEC Flows.Exp

ASIC Design Verification EngineerJob Title - ASIC Design Verification Engineer

TranSquared incCompany Name - TranSquared inc

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San Jose, California, USA

Contract

Job Title:- ASIC Design Verification Engineer Duration:-12 months+ Location:-San Jose , CA(Onsite - Work from Office 5 days per week). About the Role: We are seeking a highly skilled and motivated ASIC Design Verification Engineer with over 6 years of experience in the field of verification. As an Individual Contributor, he/she will play a crucial role in ensuring the quality and reliability of our cutting-edge ASIC designs, contributing to industry-leading innovations. Key Responsibilities: Dev

Design Verification EngineerJob Title - Design Verification Engineer

LeadStack, Inc.Company Name - LeadStack, Inc.

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No location provided

Full-time, Contract

Lead Stack Inc. is an award-winning, one of the nation's fastest-growing, certified minority-owned (MBE) staffing services provider of contingent workforce. As a recognized industry leader in contingent workforce solutions and Certified as a Great Place to Work, we're proud to partner with some of the most admired Fortune 500 brands in the world. TITLE: Design Verification Engineer LOCATION: San Jose CA/ Austin TX DURATION: 5+ Months with possible extension Rate: $90-$110/hr on W2 Job Descriptio

System IP Design Verification EngineerJob Title - System IP Design Verification Engineer

BayOne SolutionsCompany Name - BayOne Solutions

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Austin, Texas, USA

Contract

Title: Senior System IP Design Verification Engineer (Contract)Duration: Through 09/12/2025Pay: $90/hr $120/hr Job OverviewWe're looking for a Senior Staff System IP Design Verification Engineer to lead verification efforts for advanced System IP (coherent interconnects, caches). This is a hands-on role requiring deep experience in UVM, SystemVerilog, and gate-level simulation (GLS). Key ResponsibilitiesDevelop reusable testbenches and verification environments from scratch Drive best practices

MLA IP Design Verification Engineer , Annapurna LabsJob Title - MLA IP Design Verification Engineer , Annapurna Labs

Annapurna Labs (U.S.) Inc.Company Name - Annapurna Labs (U.S.) Inc.

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Cupertino, California, USA

Full-time

Job summary Amazon Web Services provides a highly reliable, scalable, low-cost infrastructure platform in the cloud that powers hundreds of thousands of businesses in 190 countries around the world. We are seeking an experienced Design Verification Engineers to build the next generation of our cloud server platforms. Our success depends on our world-class infrastructure; we're handling massive scale and rapid integration of emergent technologies. As a member of the Cloud-Scale Machine Learning

MLA IP Design Verification Engineer , Annapurna LabsJob Title - MLA IP Design Verification Engineer , Annapurna Labs

Annapurna Labs (U.S.) Inc.Company Name - Annapurna Labs (U.S.) Inc.

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Cupertino, California, USA

Full-time

Job summary Amazon Web Services provides a highly reliable, scalable, low-cost infrastructure platform in the cloud that powers hundreds of thousands of businesses in 190 countries around the world.We are seeking an experienced Design Verification Engineers to build the next generation of our cloud server platforms. Our success depends on our world-class infrastructure; we're handling massive scale and rapid integration of emergent technologies.As a member of the Cloud-Scale Machine Learning Acc

Lead, Test/Design Verification Engineer, Advanced Product VenturesJob Title - Lead, Test/Design Verification Engineer, Advanced Product Ventures

NIKECompany Name - NIKE

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Beaverton, Oregon, USA

Full-time

WHO YOU WILL WORK WITH You will work closely with the GM, Product lead, Nike Sports Research Lab lead, Engineering and Design teams, Program Management and Finance, to bring safe and reliable products to market. You will work across the Nike matrix to build support from product testing functions across the company. WHO WE ARE LOOKING FOR We are looking for a Test/Design Verification Engineering Lead to join a newly formed team developing innovative, powered athlete products. WHAT YOU BRING Bach

Design Verification EngineerJob Title - Design Verification Engineer

Della InfotechCompany Name - Della Infotech

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Mountain View, California, USA

Third Party, Contract

Strong expertise along-with complex SoC/IP debug is must At-least 5+ years of experience in System Verilog HVL and C/C++. AMBA AXI bus along-with ARM or C based processor Experience in complete verification cycle which includes development of test plan, BFM/Driver/Monitor/Scoreboard component development and integration in test bench, stress/corner testing, failure debug, gate level simulations, assertions, and coverage closure.

System IP Design Verification EngineerJob Title - System IP Design Verification Engineer

BayOne SolutionsCompany Name - BayOne Solutions

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Austin, Texas, USA

Contract

Job Title: System IP Design Verification Engineer Duration: 6 Months Location: Austin, TX, USA / San Jose, CA (Hybrid) Note: GLS verification experience, preferably on SoC designs." Good hands-on experience in debugging GLS. Must Have: Minimum 10 years of experience in verification of DV role along withHands on UVM, system Verilog and TestbenchGate Level simulation Primary skillsRTL designMajority of work will be on Gate level simulationThis will be a ands on roleNice to have: LPDDR memoryco

Design Verification EngineerJob Title - Design Verification Engineer

Avance ConsultingCompany Name - Avance Consulting

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Remote

Full-time

<>Key Responsibilities:Strong understanding of SV and UVM and good debugging skills.Understanding of AMBA protocols.Understand design specs and develop test plans based on functional and architectural requirementsBuild UVM/System Verilog-based verification environments for IP/subsystem/SoC level testingDevelop directed and random testcases, perform coverage analysis, and close functional/code coverageDebug simulation failures and work closely with RTL designers to resolve issuesExecute regressio

Senior FPGA Design Verification Engineer - Secret ClearanceJob Title - Senior FPGA Design Verification Engineer - Secret Clearance

Amarx Search, Inc.Company Name - Amarx Search, Inc.

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Dedham, Massachusetts, USA

Full-time

Amarx Search, Inc. - amarx.com Direct Hire - Full Time position in Dedham, MA Position ID: 2632 An excellent position with a major global technology solutions company * Senior FPGA Design Verification Engineer - Secret Clearance * Please apply ONLY if you have an active DOD Secret clearance and VHDL (or similar) United States Citizenship is required due to government contract requirement; we are unable to sponsor at this time. We can ONLY consider your application if you have: 1: Active DOD Sec

Design Verification EngineerJob Title - Design Verification Engineer

TecHobbitCompany Name - TecHobbit

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Remote

Contract

Title: Design Verification Engineer Location: Remote Duration: 12 months with possible extension Requirement: Good Design Verification Skill with major GLS work experience. Expertise in testbench updates for GLS Expertise in Scripting languages perl or python Experience with Make, Yaml & Json file systems. Experience with 0 delay simulations and post layout simulations with SDF back annotations (Best/Typical/Worst Case analysis). Good understanding of RTL synthesis , Static Timing Analysis &

Design Verification EngineerJob Title - Design Verification Engineer

BayOne SolutionsCompany Name - BayOne Solutions

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Austin, Texas, USA

Contract

Title - System IP Design Verification Engineer Duration 6+ Months Job ID - 429704 Location - 3900 N Capital of Texas Hwy, Austin, TX, USA OR 3655 N 1st St, San Jose, CA, USA Job Description As a Senior Staff System IP Design Verification Contractor you will contribute to the functional verification of System IP including coherent interconnect and caches. This is a technical individual contributor role with heavily involved hands-on project execution. A strong background in Design Verification

Design Verification EngineerJob Title - Design Verification Engineer

Innova Solutions, IncCompany Name - Innova Solutions, Inc

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Remote or Mountain View, California, USA

Third Party, Contract

A client of Innova Solutions is looking for an Design Verification Engineer. Position type: Contract Duration: 12+ Months Location: Mountain View, CA (Onsite Job) As a Design Verification Engineer, you will need: Minimum Qualifications: Experience in SV and UVM and good debugging skills.Understanding of AMBA protocols.Build UVM/System Verilog-based verification environments for IP/subsystem/SoC level testingDevelop directed and random testcases, perform coverage analysis, and close functional/co

Mixed-Signal Design Verification EngineerJob Title - Mixed-Signal Design Verification Engineer

Talent Junction, LLC.Company Name - Talent Junction, LLC.

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San Jose, California, USA

Contract, Third Party

Title: Mixed-Signal Design Verification Engineer Location: San Jose, CA Key Technical Skills:UVM/System Verilog, Python, Synopsys/Cadence EDA Verifications Tools, AMS Verification Required Experience/Skills: Good knowledge of System-Verilog RTL coding including state machines, adders, multipliers, combinatorial logic, etc. Good understanding of digital design for mixed signal control loops and designing Verilog / Verilog- A code to control analog circuits (e.g. bandgap, PLL, Amplifier, Filters

FPGA Design Verification EngineerJob Title - FPGA Design Verification Engineer

DBA Web TechnologiesCompany Name - DBA Web Technologies

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Dedham, Massachusetts, USA

Full-time

FPGA Design Verification Engineer (OVM - UVM design verification, FPGA - ASIC design, bash, csh, Perl, TCL, Python, VHDL, Xilinx FPGA & Questa) in Dedham, MA7+ to 10 years of experience POSITION: FPGA Design Verification Engineer (OVM - UVM design verification, FPGA - ASIC design, bash, csh, Perl, TCL, Python, VHDL, Xilinx FPGA & Questa) in Dedham, MA SECURITY CLEARANCE: Must be able to obtain Secret Security Clearance (ship is Required) LOCATION: Dedham, MA (onsite) DURATION: Full-Time Positio