design verification engineer Jobs

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Design verification Engineer

Innova Solutions, Inc

Mountain View, California, USA

Contract, Third Party

A client of Innova Solutions is immediately hiring a Design verification Engineer Position type: Contract Duration: Contract Location: Mountain View, CA (Hybrid) As a Design verification Engineer, you will need: Must-Have Skills: 9+ years of experience as Design Verification EngineerStrong understanding of SV and UVM and good debugging skills.Understanding of AMBA protocols.Understand design specs and develop test plans based on functional and architectural requirementsBuild UVM/System Verilog-

Design Verification Engineer - SoC (Associate Level)

Yoh - A Day & Zimmerman Company

Santa Clara, California, USA

Full-time

Design Verification Engineer SoC (Associate Level) We are building high-performance silicon for AI and compute-intensive workloads. We re looking for an Associate Design Verification Engineer to support SoC-level debug, triage, and verification focused on complex subsystems like PCIe and IOMMU. Scope: Perform SoC-level design verification with emphasis on debugging and triage. Work with PCIe and IOMMU/MMU, including VA to PA address translation. Analyze waveforms and root-cause functional and i

Principal Design Verification Engineer

OSI Engineering, Inc.

San Jose, California, USA

Full-time

Principal Design Verification Engineer A leading chip and silicon IP provider focused on accelerating and securing data is looking to hire an outstanding Principal Design Verification Engineer to join its Memory Interface Chip (MIC) team in San Jose, CA. This role offers the chance to work alongside top engineering talent on innovative products that push the boundaries of speed and data security. As a Principal Design Verification Engineer, you ll play a critical role in the development of MIC p

Design verification Engineer

Enfycon Inc

Remote or Mountain View, California, USA

Contract

Minimum Qualifications: Design Verification Engineering ServicesTestbench development System Verilog Universal Methodology (UVM), Python, and C testsIntegration/development of C tests/Application Programming Interface (APIs) and software build flowIntegration of UVM testbenchesTest development and debug, including without limitation tests for functionality, power, performance, error, and connectivity, both for RTL and Gate Level Netlist Design Under Test, tests for functional and code coverage

Senior Design Verification Engineer, HW Compute Group

Amazon.com Services LLC

Sunnyvale, California, USA

Full-time

The team that built the innovative Silicon IP AZ1 Neural Edge that is powering the latest generation of Echo devices is looking for a Senior Design Verification Engineer to continue to innovate on behalf of our customers. We are a part of Amazon Lab126 that revolutionized reading with our Kindle family of products and reimagined user experience through Echo and Alexa. We want you to help us build on the success of our first generation of ML accelerator at edge. Work hard. Have fun. Make history.

Senior Design Verification Engineer, HW Compute Group

Amazon.com Services LLC

Sunnyvale, California, USA

Full-time

The team that built the innovative Silicon IP AZ1 Neural Edge that is powering the latest generation of Echo devices is looking for a Senior Design Verification Engineer to continue to innovate on behalf of our customers. We are a part of Amazon Lab126 that revolutionized reading with our Kindle family of products and reimagined user experience through Echo and Alexa. We want you to help us build on the success of our first generation of ML accelerator at edge. Work hard. Have fun. Make history

Design Verification Engineer - SOC

Millennium Software, Inc.

Round Rock, Texas, USA

Contract

Millennium Software & Staffing is looking for Design Verification Engineer SOC at Round Rock, TX Below are the details: Title : Design Verification Engineer SOC Location : Round Rock, TX TOP SKILLS: SOCUVM, System VerilogIntegrate GPU, CPU, Arm Based SystemPCIe, DDR, Ethernet, Bus ProtocolsPython Scripting Candidate should have average or above average Python SkillsExperience: 8+ years of experience in SOC, SystemVerilog/UVM methodologyExperience in EDA tools and scripting (Python, TCL, Perl, Sh

Senior Design Verification Engineer - Ethernet PHY/PCS

Sivaltech

Santa Clara, California, USA

Contract, Third Party

Job Title: Senior Design Verification Engineer - Ethernet PHY/PCS Location: Santa Clara, CA Job Type: Contract, Full-time Experience: 7+ years We're seeking an experienced Senior Design Verification Engineer with expertise in Ethernet PHY or PCS to join our team in Santa Clara, CA. Responsibilities: - Develop and execute verification plans for Ethernet PHY or PCS - Create and maintain testbenches and test suites - Collaborate with design engineers to resolve verification issues - Strong understa

Design Verification Engineer

Mirafra Inc

San Jose, California, USA

Full-time

Experience: 6 to 15+ years of experience. Job Requirements are as below: Architect block and full-chip verification environments using HVLs and constrained random techniques for SOCs with embedded CPUs and mixed signal interfaces. Requires UVM, System Verilog, SVA Develop test plans and coverage metrics from specifications and write block and chip-level tests in C,SV,UVM Debug RTL and Gate simulations and work with design engineers to verify fixes. Write diagnostics for validation of FPGA prot

EDVT (Electrical Design Verification Test) Engineer

Recruitment.ai

San Jose, California, USA

Contract

Position: EDVT (Electrical Design Verification Test) Engineer Location: San Jose, CA - Onsite Role & Responsibilities:Participates on a project team of engineers involved in the specification, design, development, and test of hardware. Defines the unit and system level test processes and procedures.Performs complex system level unit and integration test. Debug/Mitigate complex system level problems.This engineer will work closely with hardware design engineers, software/diagnostic engineers, an

AI HW Design Verification Engineer

Yoh - A Day & Zimmerman Company

Remote or Santa Clara, California, USA

Full-time

AI HW Design Verification Engineer Looking for a Senior Design Verification Engineer. This person will play a key role in quality and reliability of digital designs through comprehensive verification methodologies. This person should have a strong background in verification techniques/processes, problem solving skills, and skilled at delivering high quality designs. Scope: Develop & execute comprehensive verification strategies in order to validate complex digital designs, ensuring compliance w

Design Verification Engineer

Avance Consulting

Mountain View, California, USA

Contract

Job Description Strong understanding of SV and UVM and good debugging skills. Understanding of AMBA protocols. Understand design specs and develop test plans based on functional and architectural requirements Build UVM/System Verilog-based verification environments for IP/subsystem/SoC level testing Develop directed and random testcases, perform coverage analysis, and close functional/code coverage Debug simulation failures and work closely with RTL designers to resolve issues Execute regressio

Design Verification Engineer RISC-V CPU Development

Xpeerant Incorporated

Portland, Oregon, USA

Full-time

Design Verification Engineer RISC-V CPU Development Are you passionate about cutting-edge CPU architecture and ready to take your verification skills to the next level? We re partnering with a global leader in RISC-V processor design to find talented Design Verification Engineers to join their high-impact VLSI team. You ll work alongside seasoned architects and engineers to verify next-generation RISC-V CPU cores, develop test benches from the ground up, and help shape the future of custom CPU I

Design Verification Engineer

Innova Solutions, Inc

Mountain View, California, USA

Contract

A client of Innova Solutions is immediately hiring for a Design Verification Engineer Position type: Contract Location: Mountain View, CA-Onsite As a Design Verification Engineer, you will be responsible for: Job description: Strong understanding of SV and UVM and good debugging skills.Understanding of AMBA protocols.Understand design specs and develop test plans based on functional and architectural requirements.Build UVM/System Verilog-based verification environments for IP/subsystem/SoC leve

Defense Sr. FPGA Design Verification Engineer with Secret Clearance

ZoeTech Staffing LLC

Columbia, Maryland, USA

Full-time

Job Description: Our defense client is seeking digital verification engineers to support our development of secure tactical communication products. The candidate will function primarily in an FPGA verification role, working in a cooperative team environment to verify and test embedded FPGA firmware for radio communication systems. Successful candidates must have familiarity with a coverage-driven verification methodology from planning through closure as well as knowledge of industry standard int

MLA IP Design Verification Engineer , Annapurna Labs

Annapurna Labs (U.S.) Inc.

Cupertino, California, USA

Full-time

Job summary Amazon Web Services provides a highly reliable, scalable, low-cost infrastructure platform in the cloud that powers hundreds of thousands of businesses in 190 countries around the world. We are seeking an experienced Design Verification Engineers to build the next generation of our cloud server platforms. Our success depends on our world-class infrastructure; we're handling massive scale and rapid integration of emergent technologies. As a member of the Cloud-Scale Machine Learning

MLA IP Design Verification Engineer , Annapurna Labs

Annapurna Labs (U.S.) Inc.

Cupertino, California, USA

Full-time

Job summary Amazon Web Services provides a highly reliable, scalable, low-cost infrastructure platform in the cloud that powers hundreds of thousands of businesses in 190 countries around the world.We are seeking an experienced Design Verification Engineers to build the next generation of our cloud server platforms. Our success depends on our world-class infrastructure; we're handling massive scale and rapid integration of emergent technologies.As a member of the Cloud-Scale Machine Learning Acc

Design Verification Engineer

LeadStack, Inc.

No location provided

Full-time, Contract

Lead Stack Inc. is an award-winning, one of the nation's fastest-growing, certified minority-owned (MBE) staffing services provider of contingent workforce. As a recognized industry leader in contingent workforce solutions and Certified as a Great Place to Work, we're proud to partner with some of the most admired Fortune 500 brands in the world. TITLE: Design Verification Engineer LOCATION: San Jose CA/ Austin TX DURATION: 5+ Months with possible extension Rate: $90-$110/hr on W2 Job Descriptio

AI HW Design Verification Engineer

Yoh - A Day & Zimmerman Company

Remote or Santa Clara, California, USA

Full-time

AI HW Design Verification Engineer Looking for a Senior Design Verification Engineer. This person will play a key role in quality and reliability of digital designs through comprehensive verification methodologies. This person should have a strong background in verification techniques/processes, problem solving skills, and skilled at delivering high quality designs. Scope: Develop & execute comprehensive verification strategies in order to validate complex digital designs, ensuring compliance w

Satellite or Space FPGA Design / Verification Engineer

Sun Technologies,Inc.

Remote

Contract

Job Title: Satellite or Space FPGA Design / Verification Engineer Duration: up to 3 months contract with possible extension Location: Remote Work / Work from Home Work Schedule: 5/40-1st Shift Pay Rate: $87.19/hr on W2 [the pay rate may differ depending on your skills, education, experience, and other qualifications] Featured Benefits: Medical Insurance in compliance with the ACA401(k)Sick leave in compliance with applicable state, federal, and local laws Job Description: ASIC/FPGA Engineer an