Remote
•
2d ago
5+ years of RTL design experience with DSP or compute-intensive architecturesHands-on experience with DSP pipelines, MAC engines, or custom dataflow designStrong understanding of datapath performance and throughput optimizationProficiency in Verilog / SystemVerilog with solid simulation/debug skills(Assumption: treating this as primarily an RTL-focused role please advise if HLS experience would also be helpful)
Easy Apply
Third Party, Contract
Depends on Experience








