Eda jobs in cupertino, ca

EDA/CAD Engineer (Analog & Mixed Signal)

Hybrid in Sunnyvale, California

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6d ago

EDA/CAD Engineer (Analog & Mixed Signal) Sunnyvale, CA Hybrid 3 days onsite (relocation candidates is fine) 12 Months 2 video calls Job Description: Seeking an EDA/CAD Engineer to support and develop SiGe and CMOS design solutions for the high speed analog ASIC design team. The engineer will be hands-on with all phases of tool flow including PDK installation and support, tool support and installation, layout support, design support including schematic and simulation, design archive and tapeout

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Contract

75 - 80

High-Speed EDA/CAD Engineer (Analog & Mixed Signal)

Sunnyvale, California

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6d ago

Position:High-Speed EDA/CAD Engineer (Analog & Mixed Signal) Location:Sunnyvale, CA Hybrid 3 days onsite (relocation candidates is fine) Duration:24+ month contract Domain:Analog & Mixed Signal EDA/CAD Job Description: Client is seeking an EDA/CAD Engineer to support and develop SiGe and CMOS design solutions for the high-speed analog ASIC design team. The engineer will be hands-on with all phases of tool flow, including PDK installation and support, tool support and installation, layou

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Contract

$60 - $70

Opening for Sr. Director FP&A Systems - CA

Santa Clara, California

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7d ago

We have an opening for Sr. Director FP&A Systems Location - ONSITE - Irvine, CA or Santa Clara, CA Full time permanent position Must-haves Bachelor s or Master s in Engineering, Technology, or related field. 15+ years in IT or technology leadership, including 5+ years in engineering applications or lab operations. Proven success leading large-scale standardization or transformation across global teams. Exceptional program management, stakeholder alignment, and communication skills. Less Common R

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Full-time

$180,000 - $285,000

CAE Engineer 598268

San Jose, California

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Yesterday

Job Description Title: CAE Engineer 598268 Location: San Jose, CA Description: Position Requirements: Qualifications: Bachelor's degree in Computer Engineering, Electrical Engineering, Computer Science, or a related field 3+ years of hands-on experience in HPC infrastructure, EDA/engineering IT infrastructure, or Linux system administration Working knowledge of job schedulers (LSF, SLURM, Grid Engine, or equivalent), license management systems, and engineering/EDA application environments A

Contract

CAE Engineer

San Jose, California

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Today

Job Title: "CAE Engineer" Location: San Jose, CA (Onsite) Description We are hiring a contract EDA Workflow & Infrastructure Engineer to operate the HPC compute infrastructure and engineering application environments used by our engineering and R&D organizations. The role covers hands-on deployment, monitoring, and operational support for compute clusters, application environments, license systems, and user access environments. Responsibilities: Engineering application environment operations: i

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Contract

72 - 84

Senior DevOps Engineer – HPC / EDA / SLURM

Remote

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13d ago

Role:SOFTWARE ENGINEER (Senior DevOps Engineer HPC / EDA / SLURM) Location- Remote and Rancho Cordova, CA HPC / EDA Platforms, Linux Systems Engineering & OS Deployment, multi-version Ansible playbook compatibility across SLES 12 and SLES 15 Remote (100%) W2 Only Job Description: We are seeking a Senior DevOps Engineer to provide a 3-month contingent engagement supporting our High Performance Computing (HPC) and Electronic Design Automation (EDA) infrastructure team. This role will work direct

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Contract

60 - 65

Software Architect, 3DIC P&R & AI-driven EDA Automation

San Jose, California

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Today

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. We are looking for a Software Architect to help build scalable EDA flows and AI-driven automation for advanced 3DIC applications. This role will focus on developing robust flow-generation capabilities, debugging assistance, root-cause analysis, and platform integration for 3DIC, interposer, and RDL system flows. Core Responsibilities Build scalable EDA flows using C++, Tcl, Python, and

Full-time

USD 178,500.00 - 331,500.00 per year

Senior Staff Engineer, HPC & EDA Design Infrastructure

San Jose, California

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Today

Please Note: To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period. Advancing the World's Technology Together Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you'll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries o

Full-time

USD 189,000.00 - 301,000.00 per year

Design Verification Engineer (Only W2)

Santa Clara, California

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Today

Job descriptionYour Team, Your Impact As part of the Design Verification Team at Marvell, you will verify all of the circuitry that goes inside our chips for the general market and for specific customers. These chips use cutting-edge technology to facilitate data transfers at high speeds, and you will help verify that each design meets our customers'' specifications whether they''re a major telecom organization or automotive company, etc. What You Can Expect As a leading member of the Network S

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Full-time

150,000 - 300000

Principal Software Engineer, ML

San Jose, California

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Today

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. We are seeking a highly skilled Software Engineer to join our dynamic team. The ideal candidate will have advanced experience working with large language models (LLM), machine learning (ML), and big data technologies such as Langchain and Spark. This role requires the ability to translate business requirements into both high-level and detailed technical architectures, ensuring robust an

Full-time

USD 136,500.00 - 253,500.00 per year

Remote (PST time zone preferred) -- Lead ASIC DFT Engineer

San Jose, California

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20d ago

Hello Professional, Good Afternoon Please find the job description give below, if interested please share me your most updated copy of resume. Role: Lead ASIC DFT Engineer Work Setup: Remote, PST time zone preferred Experience Required:10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary: We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep tec

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Contract, Third Party

Depends on Experience

Sr. SW Engineering Group Director

San Jose, California

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Today

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. We are seeking a seasoned leader to lead engineering teams developing industry-leading Electronic Design Automation (EDA) solutions for Static Timing Analysis (STA) technologies. The ideal candidate brings extensive leadership experience, a strong track record of delivering complex software products, and deep expertise in high-performance computing, algorithms, and semiconductor design

Full-time

USD 224,000.00 - 416,000.00 per year

Signal and Power Integrity Senior Application Engineer

San Jose, California

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Today

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. The candidate will work closely with Sales Account Managers and technical field application engineers supporting technical campaigns by delivering workshops, product demonstrations, training, and onsite support. The candidate will have expert knowledge of the Cadence tool set and/or equivalent competitor toolsets in the context of multiple flows including high speed signal design, power

Full-time

USD 84,000.00 - 156,000.00 per year

ASIC Implementation Engineer PD

San Jose, California

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Today

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Broadcom is searching for an ASIC top level floorplan Physical Design Engineer to join the Asic Products Division. This position involves working with the latest technology to continue driving next generation Artificial Intelligence and PCIe Switch Pro

Full-time

USD 121,900.00 - 195,000.00 per year

Sr. Timing Methodology Engineer

San Jose, California

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Today

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the wo

Full-time

USD 124,040.00 per year

Senior DFT Engineer

Santa Clara, California

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Today

Come be a part of new process technology adoption by joining NVIDIA's Advanced Technology Group! Work as part of the advanced technology team to optimize design tradeoffs and methodology on next generation CMOS technology. We are looking for a Senior DFT Engineer to join our dynamic and growing team! If you are problem solver and highly motivated individual searching for a collaborative and exciting role, join us today. We encourage applicants with a history of proven success working in a multic

Full-time

USD 196,000.00 - 310,500.00 per year

TFT Process Engineer

Cupertino, California

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Today

Apple is looking for world-class Thin Film Transistor (TFT) panel process engineer who will be an integral part of next Apple products. TFT process team is responsible for delivering advanced TFT panel technologies and architectures to realize world's best performance in iPad and Mac displays. Seeking individual will serve as a focal point in overseeing the unit process and integration of TFT architecture; from research, development to mass production implementation of TFT panels. This includes

Full-time

Engineering/IT Specialist

San Jose, California

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Today

Job Details: Job Description: About Altera At Altera , our independence as the world's largest pure-play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry-leading FPGA expertise, our singular mission is to deliver the programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets like AI, cloud, networking, and edge. As an independent company, we move faster,

Full-time

USD 166,900.00 - 235,000.00 per year

Senior RF Test Engineer

Milpitas, California

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Today

Join the Team That's Redefining Wireless Technology At Tarana, we're more than just a fast-growing tech company-we're a team of bold innovators on a mission to revolutionize broadband. Our groundbreaking Fixed Wireless Access technology is delivering fiber-class internet speeds worldwide, bridging the digital divide in ways previously thought impossible. Tarana is a fast revenue growth company built by outstanding talented people and with innovative technology. Our RF Team is seeking a talente

Full-time

USD 120,000.00 - 155,000.00 per year

Principal Product Engineer, Synthesis

San Jose, California

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Today

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Seeking a highly motivated engineer who can drive improvement to Cadence's synthesis and place & route products from a design perspective. The position provides an excellent opportunity to work closely with the R&D team to define the roadmap of the products. Job responsibilities: Perform Product Engineering work for Genus Synthesis Solution (Genus), a logic synthesis software used for

Full-time

USD 136,500.00 - 253,500.00 per year

Eda jobs in Cupertino, CA, USA