Lvs jobs in palo alto, ca

San Jose, California

•

Today

Job Title: Analog Layout Engineer (592074) Location: San Jose, CA (Onsite) Description As an Analog Layout Engineer, you will be responsible for: Layout of Analog / High Speed transceiver circuit blocks such as amplifiers, drivers, ADC, DAC, LDO, PLL, filters, etc. in a timely manner. Layout of sensitive active / passive components including resistors, capacitors and inductors. Design verification including DRC, LVS, ERC and ANT and extraction. Block level floor planning with design engineers. R

Full-time

Physical Design Engineer

Palo Alto, California

•

15d ago

Position: Physical Design Engineer Location : Palo Alto, CA (Full Onsite) Rate : 90-100/hr Client : HCL/Tesla Job ID : 166019 Number of Positions : 5 JD for PD: Exposure to TSMC 2NP/3NP is mustPerform endtoend physical design flow:FloorplanningPower planning (PG grid, IR)Placement & optimizationCTS (Clock Tree Synthesis)RoutingPostroute optimizationAchieve timing closure across all modes and cornersResolve DRC, LVS, ERC and signoff violationsHandle lowpower design techniques:MultiVt, Multivolta

Easy Apply

Contract

Depends on Experience

Physical Design Engineer Semiconductor / ASIC

Hybrid in Palo Alto, California

•

Today

Physical Design Engineer Semiconductor / ASIC Location: Palo Alto, CA (100% Onsite) Openings: 5 Job Overview We are looking for an experienced Physical Design Engineer with strong hands-on expertise in end-to-end ASIC physical design and advanced semiconductor process nodes. The ideal candidate must have exposure to TSMC 2NP/3NP technology and proven experience in physical implementation, timing closure, power optimization, and physical verification. Key Responsibilities Execute the complete phy

Easy Apply

Contract

$70 - $90

Sr. Engineer, Layout Design

Santa Clara, California

•

3d ago

About SiTime SiTime is the Precision Timing company. Timing is the heartbeat of all electronics, ensuring performance, resilience and scalability. For decades, quartz devices, non-silicon technology, have kept systems in sync, but they struggle in harsher, more demanding environments. MEMS-based Precision Timing delivers greater accuracy, smaller size and resilience. Today, MEMS timing powers over 400 applications, including high-growth ones in AI datacenters, automated driving, industrial and

Full-time

USD 124,920.00 - 171,770.00 per year

Staff Engineer, SRAM Circuit Design

San Jose, California

•

Today

Please Note: To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period. Advancing the World's Technology Together Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you'll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries o

Full-time

USD 163,000.00 - 253,000.00 per year

Senior Physical Verification CAD Engineer

Mountain View, California

•

Today

Overview Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft's expanding Cloud Infrastructure and responsible for powering Microsoft's "Intelligent Cloud" mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and complian

Full-time

USD 119,800.00 - 234,700.00 per year

Senior Engineer, Physical Design AI/ML

San Jose, California

•

Today

Full-time

USD 138,000.00 - 206,000.00 per year

Senior Backend Design Automation Engineer - New Process Node Enablement

San Jose, California

•

Today

Job Details: Job Description: About Altera At Altera , our independence as the world's largest pure-play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry-leading FPGA expertise, our singular mission is to deliver the programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets like AI, cloud, networking, and edge. As an independent company, we move faster,

Full-time

USD 149,100.00 - 215,925.00 per year

Senior Principal Analog Methodology Engineer

Santa Clara, California

•

Today

Description Invent the future with us. Ampere is a semiconductor design company for a new era, leading the future of computing with an innovative approach to CPU design focused on high-performance, energy efficient AI compute. As a pioneer in the new frontier of energy efficient high-performance computing, Ampere is part of the Softbank Group of companies driving sustainable computing for AI, Cloud, and edge applications. Join us at Ampere and work alongside a passionate and growing team - we'd

Full-time

USD 225,500.00 - 338,500.00 per year

Senior SRAM Layout Design Engineer

Santa Clara, California

•

Today

Job description: Manage the complete custom layout process for SRAM bitcell arrays, memory periphery, test structures, and memory macros in advanced CMOS technologies. Develop and improve floorplans for SRAM and memory blocks, covering array layout, periphery positioning, power grid design, routing channels, and macro assembly. Carry out, debug, and complete DRC, LVS, ERC, antenna, and associated physical verification checks with tools such as Calibre, ICV, or similar workflows. Support

Easy Apply

Contract, Third Party

$112 - $112

Staff Digital Physical Implementation and Integration Engineer

San Jose, California

•

Today

Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Design Engineer at Micron Technology, Inc., you will be responsible for designing and analyzing digital and analog circuits used in the development of memory products! We are engaged in develo

Full-time

USD 145,000.00 - 246,000.00 per year

ASIC Implementation Engineer PD

San Jose, California

•

Today

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Broadcom is searching for an ASIC top level floorplan Physical Design Engineer to join the Asic Products Division. This position involves working with the latest technology to continue driving next generation Artificial Intelligence and PCIe Switch Pro

Full-time

USD 121,900.00 - 195,000.00 per year

Physical Design Engineer

Palo Alto, California

•

Yesterday

JD for PD: Exposure to TSMC 2NP/3NP is mustPerform endtoend physical design flow:FloorplanningPower planning (PG grid, IR)Placement & optimizationCTS (Clock Tree Synthesis)RoutingPostroute optimizationAchieve timing closure across all modes and cornersResolve DRC, LVS, ERC and signoff violationsHandle lowpower design techniques:MultiVt, Multivoltage (UPF)Power gating, clock gatingPerform physical verification and signoff:STA (Primetime)SI / CrosstalkIR drop & EM analysisWork on advanced nodes (7

Easy Apply

Contract

Depends on Experience

Principal IP Signoff & Methodology Engineer

San Jose, California

•

Today

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL , Ethernet, NVLink, PCIe , and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-t

Full-time

USD 175,000.00 per year

Analog IC Layout Engineer

South San Francisco, California

•

Today

About Neuralink: We are creating devices that enable a bi-directional interface with the brain. These devices allow us to restore movement to the paralyzed, restore sight to the blind, and revolutionize how humans interact with their digital world. Team Description: The Brain Interfaces Soc Department delivers chip architecture and silicon implementation of neural recording and stimulation system-on-chip (SoC) for high-bandwidth brain-computer interfaces. We have crafted a team of exceptional

Full-time

USD 83,000.00 - 139,000.00 per year

Sr. Full Chip Physical Verification Engineer (Silicon Engineering)

Palo Alto, California

•

Today

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. SR. FULL CHIP PHYSICAL VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system.

Full-time

USD 175,000.00 - 280,000.00 per year

Senior Staff GPU Physical Design Engineer

Remote

•

Today

Job Description Title: Senior Staff GPU Physical Design Engineer Location: Austin, TX or San Jose, CA. onsite strongly preferred Need: GPU or high-performance SoC experience. Advanced node (?5nm). Full block ownership Position Summary We are seeking a Senior Staff GPU Physical Design Engineer for our client to work on the physical implementation of high-performance GPU and system-level IP, driving execution across synthesis, place-and-route, timing closure, and signoff for their advanced tech

Contract

Senior Integration/API architect

Palo Alto, California

•

Today

PsiQuantum's mission is to build the first useful quantum computers-machines capable of delivering the breakthroughs the field has long promised. Since our founding in 2016, our singular focus has been to build and deploy million-qubit, fault-tolerant quantum systems. Quantum computers harness the laws of quantum mechanics to solve problems that even the most advanced supercomputers or AI systems will never reach. Their impact will span energy, pharmaceuticals, finance, agriculture, transportati

Full-time

USD 165,000.00 - 185,000.00 per year

Senior RTL Design Engineer Networking ASIC / SystemVerilog / Ethernet San Diego

San Jose, California

•

9d ago

Job Title: Physical Design Engineer (STA / CTS / Floorplanning) Location: San Jose, CA Experience: 8+ Years Employment Type: Full-Time / Contract Job Description: We are looking for a skilled Physical Design Engineer with strong experience in advanced node physical implementation. The candidate will work on RTL to GDSII implementation, timing closure, and physical verification for complex semiconductor designs. Key Responsibilities: Physical design implementation including Floorplanning, Placem

Easy Apply

Contract, Third Party

Depends on Experience

CPU Integration CAD Engineer

Santa Clara, California

•

Today

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > CPU Engineering General Summary: NUVIA is now part of Qualcomm. Our mission is to reimagine silicon and create computing platforms that will transform the industry. You will have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability. As CPU Integration CAD engineer, you will buil

Full-time

USD 175,600.00 - 263,400.00 per year

Lvs jobs in Palo Alto, CA, USA