Tcl jobs in california

Seal Beach, California

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Today

Associate Systems Engineer Company: The Boeing Company Boeing Defense, Space, and Security (BDS), Space, Intelligence & Weapons Systems (SI&WS), is seeking an Associate Systems Engineer (Level 2) to support the team in Seal Beach, CA or El Segundo, CA. The Space & Mission Systems (SMS) team creates the next generation products and services for the BDS business unit. We work with proprietary customers in the development of the next-generation technologies in space. Our team focuses on rapid pr

Full-time

USD 98,600.00 - 133,400.00 per year

Engineering Intern - ASIC DFT (Spring 2027 Co-Op)

Palo Alto, California

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Today

About Rivian Rivian is on a mission to keep the world adventurous forever. This goes for the emissions-free Electric Adventure Vehicles we build, and the curious, courageous souls we seek to attract. As a company, we constantly challenge what's possible, never simply accepting what has always been done. We reframe old problems, seek new solutions and operate comfortably in areas that are unknown. Our backgrounds are diverse, but our team shares a love of the outdoors and a desire to protect it

Full-time

USD 45.00 - 51.00 per hour

Advanced Power Integrity & Power Delivery Architect

Palo Alto, California

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Today

Full-time

USD 186,000.00 - 296,000.00 per year

Principal DFT Engineer (Silicon Engineering)

Palo Alto, California

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Today

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. PRINCIPAL DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world'

Full-time

USD 220,000.00 - 355,000.00 per year

Principal DFT Engineer (Silicon Engineering)

Irvine, California

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Today

Full-time

USD 210,000.00 - 340,000.00 per year

Software Engineering Intern - Design Automation (Spring 2027 Co-Op)

Palo Alto, California

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Today

Full-time

USD 33.00 - 51.00 per hour

Physical Design Engineer Semiconductor / ASIC

Hybrid in Palo Alto, California

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Today

Physical Design Engineer Semiconductor / ASIC Location: Palo Alto, CA (100% Onsite) Openings: 5 Job Overview We are looking for an experienced Physical Design Engineer with strong hands-on expertise in end-to-end ASIC physical design and advanced semiconductor process nodes. The ideal candidate must have exposure to TSMC 2NP/3NP technology and proven experience in physical implementation, timing closure, power optimization, and physical verification. Key Responsibilities Execute the complete phy

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Contract

$70 - $90

Senior ASIC Emulation Engineer

California

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Today

Our Mission At Palo Alto Networks , we're united by a shared mission-to protect our digital way of life. We thrive at the intersection of innovation and impact, solving real-world problems with cutting-edge technology and bold thinking. Here, everyone has a voice, and every idea counts. If you're ready to do the most meaningful work of your career alongside people who are just as passionate as you are, you're in the right place. Who We Are In order to be the cybersecurity partner of choice, w

Full-time

Requirements Systems Engineer

Seal Beach, California

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Today

Job#: 3047073 Job Description: Requirements Systems Engineer Location: Seal Beach, CA (Onsite) Candidates must be able to obtain and/or maintain a Department of Defense --Top Secret clearance as a condition and continuation of employment. Role Overview We are seeking experienced Requirements Systems Engineers to support ground systems and command and control programs. The ideal candidate will be a mid-career systems engineer with experience developing, decomposing, and managing requirements

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Full-time

$70 - $120 per hour

ASIC DFT Engineer

Palo Alto, California

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Today

Full-time

Compensation information provided in the description

Systems Engineer 4

Seal Beach, California

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Today

This posting is for a contract assignment and is not a full-time employment offer with Boeing. Candidates selected for roles will be employed as contract workers through a Boeing approved 3rd party for the duration of the specified project. Regular and predictable attendance is required Work statement is a non-managerial role, non-leadership role. The Boeing Defense, Space & Security, Space Mission Systems (SMS) organization has an exciting opportunity supporting Proprietary programs and is seek

Full-time

DFT MBIST Staff Engineer

Remote

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Today

Position Summary: We are looking for a highly experienced Senior MBIST Contractor to join our SoC Design-for-Test (DFT) team. The role is focused on hands-on Memory BIST implementation using Synopsys MBIST (SMS). The ideal candidate is an independent contributor who can own the complete MBIST flow from insertion through verification, simulation, pattern generation, and Silicon bring-up with minimal supervision. Responsibilities: Perform MBIST insertion for complex SoC designs using Synopsys SMS

Contract

USD70.0/HOURLY - USD80.0/HOURLY

Design For Test (DFT) Engineer

San Jose, California

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Today

Job Description Onsite San Jose - 5 days a week Description The team is looking for a Design-for-Test contractor to test and validate the next generation Samsung chips. Candidate will be responsible to work with Front End and Physical Design teams to implement DFT and test designs which will impact the product lines for radio frequency (RF) and BlueTooth/Wireless LAN chipsets. JOB RESPONSIBILITIES: Experience with memory BIST - Siemens Tessent Flow Experience with gate-level simulation and si

Contract

CAD and PPA Methodology Engineer

San Diego, California

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Today

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > GPU ASICS Engineering General Summary: As a member of the Graphics team, the successful applicant will help develop new flows/methodologies and algorithms to improve power, performance and area (PPA) on state-of-the-art GPU cores while working closely with the graphics microarchitecture design and implementation teams. The successful candidate will possess basic understanding of RTL design and ASIC design

Full-time

USD 161,800.00 - 242,600.00 per year

Physical Design Engineer

Irvine, California

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Today

Locations:San Jose, CA / San Diego, CA / Irvine, CARequired Skills Strong experience withCadence Innovus.Expertise in the complete Physical Design cycle fromRTL to Tape-out.Hands-on experience in:SynthesisStatic Timing Analysis (STA)Timing ClosurePlace & RouteClock Tree Synthesis (CTS)FloorplanningPhysical VerificationEM/IR AnalysisStrongTCL and/or PERL scriptingskills.

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Full-time

Depends on Experience

3DExperience Application Support (ITAR)

Remote

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Today

3DExperienceApplication Support (ITAR) Cleveland, OH (Remote) Job Description: Provide support for 3DEXPERIENCE application in an ITAR (International Traffic in Arms Regulations) compliant environment. Troubleshoot application, performance, and integration issues across multiple 3DX modules specifically Enovia. Ensure all data access, handling, and operations comply with ITAR and corporate data security policies. .Hands-on experience in MQL, TCL, Java, JPO Development, APIs, Business Objects, R

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Contract, Third Party

70 - 80

Physical Design Engineer with Cadence Innovus

San Jose, California

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Today

Conduct EM/IR analysis.Strong experience with Cadence Innovus.Expertise in the complete Physical Design cycle from RTL to Tape-out.Strong TCL and/or PERL scripting skills.Develop and optimize Clock Tree Synthesis (CTS), including custom clock trees, insertion delay reduction, and skew balancing.Perform timing closure using various methodologies and strategies, including top-level STA.Collaborate closely with IC Design and RTL Engineering teams.

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Full-time

Depends on Experience

CPU RTL Methodology Engineer

Santa Clara, California

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Today

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > CPU Engineering General Summary: We are seeking a highly skilled and versatile engineer who thrives at the intersection of RTL design and CAD automation. This role is ideal for someone who understands RTL workflows deeply and can build scalable automation solutions to streamline design and debug processes. You'll work closely with CPU design teams to support RTL development, triage issues, and enhance prod

Full-time

USD 198,700.00 - 298,100.00 per year

CPU DFT Engineer

Santa Clara, California

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Today

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > CPU Engineering General Summary: As a DFT Engineer you will work with chip architects, chip designers, implementation engineers and test engineers to verify the DFT and DFD (Design for Debug) architecture, implementation, and test plans for both mixed signal and digital VLSI designs. Then you'll insure it becomes reality. We're doing a ground up implementation of a new chip architecture, so you'll have to

Full-time

USD 142,200.00 - 213,400.00 per year

ASIC Engineering Technical Leader

San Jose, California

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Role: ASIC Engineering Technical Leader Location: San Jose, CA (Onsite) Start Date: Immediate Type: Contract (C2C/W2) Interview: Phone/Video We are seeking an ASIC Engineering Technical Leader with strong expertise in DesignforTest (DFT) for nextgen optical communication ASICs. Responsibilities include DFT architecture implementation, scan insertion, ATPG pattern generation, silicon debug, integration/verification of DFT fabrics, gatelevel simulations, and automation using Python/Tcl/C++.

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Full-time, Part-time, Contract, Third Party

Tcl jobs in California, USA