timing closure jobs in california

Immediate opening for experienced Physical Design Engineers with strong STA and timing closure experience.

San Diego, California

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23d ago

Job Title: Physical Design Engineer (STA / CTS / Floorplanning) Location: Bayarea,CA Experience: 8+ Years Employment Type: Full-Time / Contract Job Description: We are looking for a skilled Physical Design Engineer with strong experience in advanced node physical implementation. The candidate will work on RTL to GDSII implementation, timing closure, and physical verification for complex semiconductor designs. Key Responsibilities: Physical design implementation including Floorplanning, Placemen

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Full-time, Third Party

Depends on Experience

Senior STA Engineer

Remote

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10d ago

RESPONSIBILITIES - Perform static timing analysis (STA) for the PCIe subsystem within the Sparta architecture. - Develop, validate, and maintain PCIe-specific timing constraints (SDC) and exceptions. - Run fullchip and blocklevel STA for PCIe paths across PVT corners and operating modes. - Identify timing violations and drive ECO recommendations to close setup/hold, DRV, and noise issues. - Collaborate with RTL, synthesis, PnR, and verification teams to ensure endtoend PCIe timing signoff. - Ana

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Contract

80 - 90

Principal RTL Lead – High-Speed Ethernet (ASIC)

San Francisco, California

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3d ago

Principal RTL Lead High-Speed Ethernet (ASIC)Introduction:We are seeking an experienced Principal RTL Lead to drive the design and verification of next-generation Ethernet subsystems for custom ASIC silicon. This role is central to building architectures that support 400G, 800G, and beyond, enabling ultra-low latency and high reliability in large-scale data centers. As the technical lead, you will guide a team of designers through complex challenges such as multi-lane alignment, Forward Error C

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Contract, Third Party

100 - 120

Verilog Design Engineer

Remote

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27d ago

ob Title: Senior Verilog Design EngineerJob SummaryWe are looking for a Senior Verilog Design Engineer with 10+ years of experience in RTL design and digital hardware development. The ideal candidate should have strong expertise in ASIC/FPGA design flows, micro-architecture development, and SoC environments, with exposure to PCIe design or verification. Key ResponsibilitiesDevelop and implement RTL using Verilog for ASIC/FPGA platforms. Define micro-architecture and perform RTL coding, simulatio

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Contract

Depends on Experience

ASIC Implementation Engineer

San Jose, California

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Today

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Broadcom is looking for an ASIC Implementation Engineer with demonstrated expertise in multiple disciplines including synthesis, design for test, floorplanning, place and route, clock methodology, power planning and analysis, timing closure, signal int

Full-time

USD 141,300.00 - 226,000.00 per year

Staff Full-Chip Timing Engineer

San Jose, California

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Today

Looking for an Innovative Staff Full-Chip Timing (STA) Engineer - On Site This Jobot Job is hosted by: Lindsey Cusic Are you a fit? Easy Apply now by clicking the "Apply Now" button and sending us your resume. Salary: $175,000 - $235,000 per year A bit about us: We are a growing semiconductor design organization focused on advanced ASIC and SoC development. Our team is built around deep technical expertise, fast execution, and a strong ownership mindset. We work on complex, high-performance

Full-time

USD 175,000.00 - 235,000.00 per year

PNR Applications Engineer, Staff

Sunnyvale, California

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Today

Descriptions & Requirements Job Description and Requirements We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. Business Area Description: O

Full-time

Sr. FPGA Design Engineer / DSP / ASIC / Vivado IDE / Onsite / Irvine

Irvine, California

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Today

A well-established security company that helps build technology to help protect our communities. Their technology is pivotal to creating software that helps create safer schools, hospitals and ultimately a safer nation. They are currently looking for several FPGA Design Engineers. The successful individual in this role will participate in all aspects of the research and development process from concept to field deployment. FPGA Design Engineers are responsible for the efficient implementation of

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Full-time

$140000 - $200000

Engineer Digital 3

San Diego, California

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Today

Job Description Job Title: Engineer Digital 3 Location: San Diego, CA Zip Code: 92128 Duration: 6 Months Pay Rate: $54.48-$133.33/hr. Keyword's: #SanDiegojobs; #Engineerjobs. Start Date: Immediate Job Description: Responsibilities: * Design, develop, integrate and test VHDL-based digital designs for our end-user customers and businesses, primarily focused on software defined radio VHDL firmware code bases. * Work using FPGA programming development tools and environments * Work with multi-discip

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Full-time

Compensation information provided in the description

Sr Principal Application Engineer

San Jose, California

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Today

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Description Summary The Senior Principal Application Engineer will be a trusted technical leader, driving complex pre-sales and post-sales engagements for Cadence Digital IC products at advanced nodes. This role demands a proven ability to solve the toughest design challenges and deliver innovative solutions that ensure customer success. Key Responsibilities Lead technical strateg

Full-time

USD 143,500.00 - 266,500.00 per year

Emulation Methodology Engineer

San Diego, California

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Today

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. Qualcomm's Emulation Team is part of the central SoC digital hardware organization responsible for the overall development and support of SoC

Full-time

USD 140,000.00 - 210,000.00 per year

Engineer Digital 3

San Diego, California

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Today

Location: San Diego, CA Salary: $80.00 USD Hourly - $125.00 USD Hourly Description: Position: Digital Engineer (FPGA / VHDL) Location: San Diego, CA About the Role We are seeking a Digital Engineer to join a mission-focused engineering team working on advanced digital systems. In this role, you will design, develop, integrate, and test FPGA-based solutions that support next-generation, software-defined radio and communication systems. You will collaborate closely with cross-functional engine

Contract

Compensation information provided in the description

Application Engineer Architect

San Jose, California

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Today

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Overview The Architect will serve as a technical leader within Cadence's North America Field Applications Team, driving strategic customer engagements and influencing next-generation EDA & Agentic-AI solutions. This role demands exceptional technical depth, hands-on experience of design convergence, and the ability to align cross-functional teams toward delivering advanced design solut

Full-time

USD 157,500.00 - 292,500.00 per year

Application Engineer, RTL2GDS Architect

San Jose, California

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Today

Full-time

USD 157,500.00 - 292,500.00 per year

Senior Electrical Engineer - ASIC/FPGA Mission Systems (Onsite)

El Segundo, California

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Today

Date Posted: 2026-03-05 Country: United States of America Location: US-CA-EL SEGUNDO-E01 ~ 2000 E El Segundo Blvd ~ BLDG E01 Position Role Type: Onsite U.S. Citizen, U.S. Person, or Immigration Status Requirements: Active and transferable U.S. government issued security clearance is required prior to start date.Security Clearance Type: DoD Clearance: Secret Security Clearance Status: Active and existing security clearance required on day 1 Joining Collins Aerospace isn't just about finding a

Full-time

USD 95,500.00 per year

Senior FPGA / RTL Design Engineer - Signal Processing

Los Angeles, California

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Today

Company Overview At Motorola Solutions, we believe that everything starts with our people. We're a global close-knit community, united by the relentless pursuit to help keep people safer everywhere. We build and connect technologies to help protect people, property and places. Our solutions foster the collaboration that's critical for safer communities, safer schools, safer hospitals, safer businesses, and ultimately, safer nations. Connect with a career that matters, and help us build a safer

Full-time

USD 125,000.00 - 195,000.00 per year

Physical Design Engineer

San Diego, California

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Today

Job#: 3027134 Job Description: Physical Design Engineer - Wireless RF Silicon Location: San Diego, CA Type: Contract Role Overview The client is developing next-generation silicon to power a global Low Earth Orbit (LEO) satellite communications network. The Wireless RF Silicon team is seeking a Physical Design Engineer to drive backend implementation and physical closure of complex, high-performance SoCs used in advanced wireless and RF systems.In this role, you will partner closely with RTL,

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Full-time

Senior Electrical Engineer - ASIC/FPGA (Hybrid)

Remote or Salt Lake City, Utah

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Today

Date Posted: 2026-01-28 Country: United States of America Location: US-UT-SALT LAKE CITY-547 ~ 600 Komas Dr ~ KOMAS Position Role Type: Hybrid U.S. Citizen, U.S. Person, or Immigration Status Requirements: This job requires a U.S. Person. A U.S. Person is a lawful permanent resident as defined in 8 U.S.C. 1101(a)(20) or who is a protected individual as defined by 8 U.S.C. 1324b(a)(3). U.S. citizens, U.S. nationals, U.S. permanent residents, or individuals granted refugee or asylee status in the

Full-time

USD 86,800.00 per year

ASIC Timing and Methodology Engineer

San Diego, California

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Today

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: As a Timing Engineer, you will play a vital role in Timing analysis targeting the Mobile, Compute, Automotive and IOT markets The candidate will work with best-in-class methodologies, tools and technology to design innovative SOC products at the block/IP-level and at system-level in 5nm, 4nm and beyond (process technologies).You will be working with physical design team (an

Full-time

USD 140,000.00 - 210,000.00 per year

Engineering - Engineer Digital 3

San Diego, California

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Today

Job#: 3021400 Job Description: Digital Engineer - FPGA / VHDL (On-Site, San Diego, CA) Telecommute: No - On-site only Clearance: None required (DoD Secret preferred) Schedule: 1st Shift (9/80 schedule) Travel: None Starting Pay Rate: $75.00/hr Position Overview A leading defense and technology contractor is seeking a highly skilled Digital Engineer to support FPGA-based development efforts for advanced communication and embedded systems. This role centers on VHDL firmware development for

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Full-time

USD 75.00 per hour

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timing closure jobs in California, USA