Timing closure jobs in niskayuna, ny

Remote

•

Today

Requirements please see these key words of in the project description for the profile consideration. "SCAN, ATPG, MBIST, Timing Simulations, SDF, SDC , PSV, Diagnosys , Pattern Retargeting , Pattern porting, DRCs, TetraMax, DFTMax " Experience 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requir

Full-time

Senior Principal ASIC FPGA Engineer

Remote or Boise, Idaho

•

Today

Basic Qualifications Education Requirements: Bachelor's degree in Electrical or Computer Engineering, or a related Science, Engineering or Mathematics field, plus a minimum of 10 years of relevant experience; or Master's degree plus a minimum of 8 years of relevant experience. Clearance Requirements: Ability to obtain a Department of Defense Secret security clearance is required at time of hire. Applicants selected will be subject to a U.S. Government security investigation and must meet eli

Full-time

USD 191,146.00 - 212,053.00 per year

System FPGA Engineer

Remote or Utah

•

Today

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > Systems Engineering General Summary: Job Description Our Mission We are dedicated to transforming the industry by reimagining silicon and developing next-generation computing platforms. By joining our team, you'll collaborate with world-class engineers to create innovative solutions that push the limits of performance, energy efficiency, and scalability. Our focus is on developing reference platforms based

Full-time

USD 146,400.00 - 219,600.00 per year

Lead RTL/FPGA Design Engineer

Remote

•

Today

About Aalyria: Aalyria is a leading technology company that supplies laser communications technology and temporospatial software-defined networking platforms to the aerospace industry. With technology acquired from Google, Aalyria is at the forefront of innovation in satellite and airborne mesh networks, as well as cislunar and deep-space communications. We are revolutionizing the orchestration and management of planetary mesh networks using any radio or optical spectrum, any orbit, and any har

Full-time

USD 170,000.00 - 195,000.00 per year

FPGA Design - Lead Research Engineer "CLEARANCE REQUIRED"

Niskayuna, New York

•

Today

Job Description SummaryAs an FPGA Design Research Engineer, you will have the opportunity to architect and develop state-of-the-art embedded systems for real-time controls and industrial communication applications. You will lead and contribute to R&D projects that are aligned with GE Vernova?s energy businesses such as Renewables, Gas Power, Power Conversion, Hydro, and Grid Solutions. Moreover, you will have the opportunity to shape, pursue, and execute R&D efforts in partnership with U.S. Gove

Full-time

Compensation information provided in the description

Lead ASIC DFT Engineer

Remote

•

21d ago

Role: Lead ASIC DFT Engineer Location: Remote, (Onsite) Duration: Contract Year of Exp: 10+ yrs to 15 yrs. Job Description: We are seeking a highly experienced Lead ASIC DFT Engineerto architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug efforts a

Easy Apply

Third Party, Contract

110 - 120

ASIC DFT Staff Engineer

Remote

•

Today

Job Title: ASIC DFT Staff Engineer Location: Remote Job Description: Key Skills: "SCAN, ATPG, MBIST, Timing Simulations, SDF, SDC , PSV, Diagnosys , Pattern Retargeting , Pattern porting, DRCs, TetraMax, DFTMax " Experience: 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary: We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical own

Easy Apply

Third Party, Contract

Senior Staff GPU Physical Design Engineer

Remote

•

Today

Job Description Title: Senior Staff GPU Physical Design Engineer Location: Austin, TX or San Jose, CA. onsite strongly preferred Need: GPU or high-performance SoC experience. Advanced node (?5nm). Full block ownership Position Summary We are seeking a Senior Staff GPU Physical Design Engineer for our client to work on the physical implementation of high-performance GPU and system-level IP, driving execution across synthesis, place-and-route, timing closure, and signoff for their advanced tech

Contract

FPGA Design - Lead Research Engineer "CLEARANCE REQUIRED"

Niskayuna, New York

•

Today

Job Description Summary As an FPGA Design Research Engineer, you will have the opportunity to architect and develop state-of-the-art embedded systems for real-time controls and industrial communication applications. You will lead and contribute to R&D projects that are aligned with GE Vernova's energy businesses such as Renewables, Gas Power, Power Conversion, Hydro, and Grid Solutions. Moreover, you will have the opportunity to shape, pursue, and execute R&D efforts in partnership with U.S. Gov

Full-time

USD 98,400.00 - 164,000.00 per year

Timing closure jobs in Niskayuna, NY, USA