Timing closure jobs in san francisco, ca

San Francisco, California

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Today

Join the leader in entertainment innovation and help us design the future. At Dolby, science meets art, and high tech means more than computer code. As a member of the Dolby team, you'll see and hear the results of your work everywhere, from movie theaters to smartphones. We continue to revolutionize how people create, deliver, and enjoy entertainment worldwide. To do that, we need the absolute best talent. We're big enough to give you all the resources you need, and small enough so you can make

Full-time

USD 137,100.00 - 188,300.00 per year

Staff Electrical Engineer - FPGA / MPSoC Systems & Digital Signal Processing

San Leandro, California

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Today

About SirenOpt SirenOpt helps manufacturers make better, safer, and more reliable micro- and nano-materials. These materials are the building blocks of critical sectors of the global economy such as batteries, computer chips, aircraft components, and power systems. But, surging material demand and growing complexity are pushing production to unprecedented scales and speeds, leaving manufacturers effectively flying blind. Small, undetected variations during production lead to wastage, lower perf

Full-time

USD 160,000.00 - 240,000.00 per year

FPGA Engineer

Burlingame, California

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Today

Xona is the navigational intelligence company bringing real-time, centimeter-level certainty to any device, anywhere on Earth. With Pulsar - the world's most advanced PNT satellite infrastructure in Low Earth Orbit - Xona will offer a future-proof, backwards-compatible global positioning system optimized for absolute precision, superior power, and robust protection. We're seeking an FPGA Engineer to design and implement high-performance, signal-processing solutions for next-generation LEO PNT

Full-time

USD 100,000.00 - 140,000.00 per year

Asics Engineer

Remote

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Today

Requirements please see these key words of in the project description for the profile consideration. "SCAN, ATPG, MBIST, Timing Simulations, SDF, SDC , PSV, Diagnosys , Pattern Retargeting , Pattern porting, DRCs, TetraMax, DFTMax " Experience 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requir

Full-time

Senior Principal ASIC FPGA Engineer

Remote or Boise, Idaho

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Today

Basic Qualifications Education Requirements: Bachelor's degree in Electrical or Computer Engineering, or a related Science, Engineering or Mathematics field, plus a minimum of 10 years of relevant experience; or Master's degree plus a minimum of 8 years of relevant experience. Clearance Requirements: Ability to obtain a Department of Defense Secret security clearance is required at time of hire. Applicants selected will be subject to a U.S. Government security investigation and must meet eli

Full-time

USD 191,146.00 - 212,053.00 per year

System FPGA Engineer

Remote or Utah

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Today

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > Systems Engineering General Summary: Job Description Our Mission We are dedicated to transforming the industry by reimagining silicon and developing next-generation computing platforms. By joining our team, you'll collaborate with world-class engineers to create innovative solutions that push the limits of performance, energy efficiency, and scalability. Our focus is on developing reference platforms based

Full-time

USD 146,400.00 - 219,600.00 per year

Lead RTL/FPGA Design Engineer

Remote

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Today

About Aalyria: Aalyria is a leading technology company that supplies laser communications technology and temporospatial software-defined networking platforms to the aerospace industry. With technology acquired from Google, Aalyria is at the forefront of innovation in satellite and airborne mesh networks, as well as cislunar and deep-space communications. We are revolutionizing the orchestration and management of planetary mesh networks using any radio or optical spectrum, any orbit, and any har

Full-time

USD 170,000.00 - 195,000.00 per year

Senior Emulation Engineer

San Francisco, California

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2d ago

Senior Emulation EngineerExperience: 8+ Years Location: Bay Area, CA Duration: Long Term Contract Key skills: palladium or veloce or zebu, timing closure, PCIe, usb Job DescriptionWe are looking for a Senior Emulation Engineer with strong experience in hardware emulation and SoC/ASIC verification. Required Skills8+ years of experience in Hardware Emulation / SoC VerificationHands-on experience with Cadence Palladium, Siemens Veloce, or Synopsys ZeBuStrong experience in emulation bring-up, debugg

Easy Apply

Contract, Third Party

Depends on Experience

ASIC/ SoC RTL Design Engineer

Hybrid in Burlingame, California

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3d ago

Title: ASIC/SoC RTL Design Engineer Location: Palo Alto, CA (Or potentially Burlington, MA) Length of Contract: 6 months+ (Temp-to-Perm) Ideal Start: 6/1/2026 Responsibilities : Own end-to-end design of complex SoC subsystems, driving architecture, RTL implementation, and tapeout. Focus on high-performance Datapath, PPA optimization, and cross-functional integration across silicon, firmware, and system teams. Must haves: 8 12+ years in ASIC/SoC digital design with hands-on RTL ownershipStrong Sy

Easy Apply

Contract

$83 - $93

Lead ASIC DFT Engineer

Remote

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20d ago

Role: Lead ASIC DFT Engineer Location: Remote, (Onsite) Duration: Contract Year of Exp: 10+ yrs to 15 yrs. Job Description: We are seeking a highly experienced Lead ASIC DFT Engineerto architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug efforts a

Easy Apply

Third Party, Contract

110 - 120

ASIC DFT Staff Engineer

Remote

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Today

Job Title: ASIC DFT Staff Engineer Location: Remote Job Description: Key Skills: "SCAN, ATPG, MBIST, Timing Simulations, SDF, SDC , PSV, Diagnosys , Pattern Retargeting , Pattern porting, DRCs, TetraMax, DFTMax " Experience: 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary: We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical own

Easy Apply

Contract, Third Party

Senior Staff GPU Physical Design Engineer

Remote

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Today

Job Description Title: Senior Staff GPU Physical Design Engineer Location: Austin, TX or San Jose, CA. onsite strongly preferred Need: GPU or high-performance SoC experience. Advanced node (?5nm). Full block ownership Position Summary We are seeking a Senior Staff GPU Physical Design Engineer for our client to work on the physical implementation of high-performance GPU and system-level IP, driving execution across synthesis, place-and-route, timing closure, and signoff for their advanced tech

Contract

Timing closure jobs in San Francisco, CA, USA