Verification and validation jobs in wisconsin

Senior Verification and Validation Engineer

Madison, Wisconsin

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Today

Give hope. Give health. Make your mark in the fight against cancer. At Accuray, we make a direct and powerful impact on the lives of cancer patients every day - helping them live longer, better lives. But our commitment to innovation offers a truly unique opportunity: the chance to change the fight against cancer - helping to develop, introduce and support new treatment delivery systems and software that will give new hope and new health to cancer patients and cancer survivors around the world.

Full-time

Design Verification Engineer

Remote

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4d ago

Hi - Full Time Role Job Title: Design Verification Engineer -Performance Modelling Location : Remote USA Strong understanding of SV and UVM and good debugging skills.Understand design specs and develop test plans based on functional and architectural requirementsBuild UVM/System Verilog-based verification environments for IP/subsystem/SoC level testingDevelop directed and random testcases, perform coverage analysis, and close functional/code coverageDebug simulation failures and work closely wi

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Full-time

Depends on Experience

Sr Staff Engineer - Verification, CI/CD Infrastructure & Embedded Hardware (AISW)

Remote or California

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Today

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > Machine Learning Engineering General Summary: The Sr Staff Engineer Engineer, Verification (CI/CD & Embedded HW) is a senior individual contributor responsible for designing, scaling, and hardening CI/CD infrastructure and verification systems that validate Qualcomm's AI Software stack-including QNN HTP, QAIRT, toolchains, kernels, and embedded runtime components. This role is deeply technical and hands-on:

Full-time

USD 185,900.00 - 278,900.00 per year

Design Verification Engineer

Remote

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5d ago

Design Verification (DV) Engineer Key Responsibilities Develop and maintain UVM-based SystemVerilog testbenchesCreate reusable verification components and environmentsDevelop and execute verification plans for subsystem and block levelDebug RTL issues and collaborate closely with designContribute to end-to-end validation flowsDrive coverage closureRequired Qualifications Strong hands-on expertise in UVM and SystemVerilogExperience with ARM-based protocols including:APBAXI (no CHI/coherency requi

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Contract

Depends on Experience

Verification and validation jobs in Wisconsin, USA