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Remote (PST time zone preferred) -- Lead ASIC DFT Engineer

Tanisha Systems, Inc.

San Jose, California • 24d ago

Easy Apply

Contract, Third Party

Depends on Experience

DFT Engineer

Reveille Technologies

Mountain View, California • 3d ago

Easy Apply

Full-time, Third Party

Depends on Experience

DFT Engineer

Plugins Inc

Santa Clara, California • 2d ago

Easy Apply

Third Party, Contract

80 - 100

DFT Engineer

Goldenpick Technologies LLC

San Jose, California • Yesterday

Easy Apply

Contract, Third Party

Depends on Experience

DFT Engineer

select minds

Santa Clara, California • Today

Full-time

Compensation information provided in the description

DFT Engineer

CA-One Tech Cloud Inc.

San Jose, California • Today

Easy Apply

Third Party, Contract

$70 - $80

DFT Engineer Scan / ATPG / MBIST

Info Way Solutions

Santa Clara, California • Today

Easy Apply

Contract

Depends on Experience

Senior DFT Engineer

NVIDIA Corporation

Santa Clara, California • Today

Full-time

USD 196,000.00 - 310,500.00 per year

DFT Engineer

CompNova

Santa Clara, California • 10d ago

Easy Apply

Contract

Depends on Experience

CPU DFT Engineer

J VERS LLC

Santa Clara, California • Yesterday

Full-time

USD 142,200.00 - 213,400.00 per year

DFT Engineer

VentureSoft Global

Hybrid in San Jose, California • 11d ago

Easy Apply

Contract

Depends on Experience

Principal DFT Engineer (Silicon Engineering)

SpaceX

Palo Alto, California • Today

Full-time

USD 220,000.00 - 355,000.00 per year

ASIC/SOC DFT Engineer (Silicon Engineering)

SpaceX

Palo Alto, California • Today

Full-time

USD 135,000.00 - 175,000.00 per year

DFT Lead Engineer

Broadcom Corporation

San Jose, California • Today

Full-time

USD 143,800.00 - 230,000.00 per year

Senior DFT Engineer (Einfochips)

Arrow Electronics, Inc.

San Jose, California • Today

Full-time

Lead ASIC DFT Engineer

SAPSOL Technologies Inc.

Remote • Today

Full-time

Senior DFT Engineer

K2 Space

Remote • Today

Full-time

USD 170,000.00 - 250,000.00 per year

Sr. ASIC DFT Engineer (Silicon)

SpaceX

Palo Alto, California • Today

Full-time

USD 175,000.00 - 280,000.00 per year

DFT Engineers

E-Solutions, Inc.

Santa Clara, California • 8d ago

Easy Apply

Full-time, Third Party

Depends on Experience

Physical Design Engineer II (IC)

Arrow Electronics, Inc.

San Jose, California • Today

Full-time

Compensation information provided in the description

Senior DFT Engineer

E-Space

Saratoga, California • Today

Full-time

USD 120,000.00 - 220,000.00 per year

Asics Engineer

SAPSOL Technologies Inc.

Remote • Today

Full-time

CPU DFT Verification Engineer

Apple, Inc.

Santa Clara, California • Today

Full-time

ASIC DFT Engineer

Broadcom Corporation

San Jose, California • Today

Full-time

Hiring: DFT Lead | 7nm & Below | Saratoga, CA | Full-Time

VortexLink

Saratoga, California • 3d ago

Easy Apply

Full-time

Depends on Experience

DFT Staff Engineer

AMD (Advanced Micro Devices)

Santa Clara, California • Today

Full-time

USD 145,600.00 per year

CPU DFT Engineer

Qualcomm Technologies

Santa Clara, California • Today

Full-time

USD 142,200.00 - 213,400.00 per year

Job Details

Skills

Summary

Hello Professional,

Good Afternoon!!!

Please find the job description give below, if interested please share me your most updated copy of resume.

Role: Lead ASIC DFT Engineer
Work Setup: Remote, PST time zone preferred
Experience Required:

10+ years of hands-on experience in ASIC Design-for-Test (DFT)

Role Summary:
We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug efforts and drive resolution of critical silicon issues.

Key Pointers

DFT Architecture definition.
Scan & compression(EDT) implementation
LBIST implementation and verification
Coverage improvements (Spyglass work)
ATPG sims - timing & no timing.
Full chip / Sub system level DFT activities.

Key Skills Required:

Strong hands-on ASIC DFT experience with end-to-end ownership
Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug
Experience with Synopsys, Cadence, and Siemens/Mentor EDA tools
Strong background in scan insertion, scan chain stitching, ATPG setup, simulation, debug, and DRC analysis
MBIST implementation and verification; SMS experience preferred
Tessent/SSN experience preferred
Strong understanding of PLLs, RTL design, synthesis, LEC, and physical design flows
Post-silicon debug and silicon bring-up experience

TCL, PERL, or Python scripting experience is highly preferred

Shivam Maheshwari
Talent Acquisition Manager, Tanisha Systems Inc
ISO Certified Company{ ISO 9001:2015}
Office:
Email:
Address:99 Wood Ave South, Suite # 308, Iselin, NJ 08830

Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.

Dice Id: 10117909
Position Id: 26-17500
Posted 24 days ago

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Senior DFT EnginnerSan Jose, CAPosition Summary We are looking for a highly experienced Senior MBIST Contractor to join our SoC Design-for-Test (DFT) team. The role is focused on hands-on Memory BIST implementation using Synopsys MBIST (SMS). The ideal candidate is an independent contributor who can own the complete MBIST flow from insertion through verification, simulation, pattern generation, and Silicon bring-up with minimal supervision.Responsibilities Perform MBIST insertion for complex SoC

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Hi, Job Title : Senior DFT Engineer [ATPG , MBIST, IO Test, Clock Verification] Location : Santa Clara, CA Experience : 4+ Years in DFT Required Skills & Qualifications 4+ years of hands-on experience in DFT and ATPGfor SoC or ASIC designsStrong understanding of DFT fundamentalsincluding controllability, observability, and scan-based testingProven expertise in ATPG pattern generation, analysis, and debugExperience with MBIST, including memory test architectures and diagnosticsKnowledge of IO Tes

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Job Details

Skills

Summary

10+ years of hands-on experience in ASIC Design-for-Test (DFT)

DFT Architecture definition.
Scan & compression(EDT) implementation
LBIST implementation and verification
Coverage improvements (Spyglass work)
ATPG sims - timing & no timing.
Full chip / Sub system level DFT activities.

Key Skills Required:

Strong hands-on ASIC DFT experience with end-to-end ownership
Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug
Experience with Synopsys, Cadence, and Siemens/Mentor EDA tools
Strong background in scan insertion, scan chain stitching, ATPG setup, simulation, debug, and DRC analysis
MBIST implementation and verification; SMS experience preferred
Tessent/SSN experience preferred
Strong understanding of PLLs, RTL design, synthesis, LEC, and physical design flows
Post-silicon debug and silicon bring-up experience

TCL, PERL, or Python scripting experience is highly preferred

Shivam Maheshwari
Talent Acquisition Manager, Tanisha Systems Inc
ISO Certified Company{ ISO 9001:2015}
Office:
Email:
Address:99 Wood Ave South, Suite # 308, Iselin, NJ 08830

Dice Id: 10117909
Position Id: 26-17500
Posted 24 days ago

Fitment

Dice Job Match Score™

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