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Role: ATPG Engineer Location : Austin, TX Duration:12+ Months Perform block-level scan insertion, ATPG, coverage analysis, and simulations Run top-level test pattern retargeting and simulations Identify design changes needed for improving test coverage Skills: Expertise in ATPG, coverage analysis, and zero-delay / SDF-based pattern simulations. Experience with Mentor DFT tools (Tessent Shell) is a must. Good knowledge of Verilog, logic design, circuit design fundamentals Working knowledge o
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