Experience : 8+ Block-level physical implementation from RTL to GDSII, focusing on timing, power, and area (PPA) optimization for high-speed SerDes and interconnect subsystems. Architect implementation strategies for high performance RISC-V cores, supporting complex clock/power domains and floorplans. Collaborate with RTL, STA, and verification teams to ensure timing and physical convergence. Own advanced physical design tasks including: EM/IR and power grid optimization for high-current b