PD Engineer

Overview Do you have a passion for advanced silicon signoff and physical verification at leading-edge technology nodes? You will be part of a team responsible for driving state-of-the-art Physical Verification CAD solutions for Microsoft's silicon design teams. In this role, you will foster the enablement and support of advanced-node DRC, LVS, Antenna, and ESD signoff flows, working closely with EDA vendors, and internal design teams. You will own PV signoff methodology end to end, identify gap

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Duties: Utilizing engineering background, provide pre-sales and/or post-sales technical customer support including implementation, training, and maintenance support for Electronic Design Automation (EDA) and semiconductor intellectual property (IP). Provide technical pre-sales of High-Speed Interface IP.Present Cadence's IP portfolio and capabilities to prospective customers.Work cl

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Duties: Research, design, develop, and test electronic components and systems for Electronic Design Automation (EDA) and semiconductor intellectual property (IP) employing knowledge of electronic theory and materials properties.Utilize graduate-level research and analysis skills to perform Static Timing Analysis (STA), glitch, and noise analysis using Tempus Signoff tool.Work on SDC

Company: Qualcomm Atheros, Inc. Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: Qualcomm-Atheros, a.k.a. QCA is a wholly owned subsidiary of Qualcomm and a leading provider of wireless technologies for the mobile, networking, computing and consumer electronics markets. As a key member of a fast-paced Integrated Wireless Technology team. The role involves ownership and leading Static timing closure and synthesis for complex low-power WiFi SoCs and sub-syste