PD Engineer

San Francisco, CA, US • Posted 5 days ago • Updated 4 hours ago

Full Time

On-site

Fitment

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Job Details

Skills

Pure Data
SERDES
Collaboration
RTL
Static Timing Analysis
International Relations
Investor Relations
Information Retrieval
GRID
Optimization
Routing
Timing Closure
Management
LVS
Antennas
ICC
calibre
Physical Data Model
Tcl
Python
Perl
Scripting

Summary

Experience : 8+
Block-level physical implementation from RTL to GDSII, focusing on timing, power, and area (PPA) optimization for high-speed SerDes and interconnect subsystems.
Architect implementation strategies for high performance RISC-V cores, supporting complex clock/power domains and floorplans.
Collaborate with RTL, STA, and verification teams to ensure timing and physical convergence.
Own advanced physical design tasks including:
- EM/IR and power grid optimization for high-current blocks
- Congestion mitigation and routing-aware floorplanning
- RC-aware timing closure across corners and PVTs
- Clock tree synthesis and skew management across domains .
Drive signoff closure: DRC, LVS, antenna, ERC, and tapeout readiness using industry-standard tools (e.g., Innovus, ICC2, Calibre, Voltus, RedHawk).
Contribute to and improve physical design automation infrastructure using Tcl, Python, Perl, and other scripting tools.

Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.

Dice Id: 91160181
Position Id: ba0f19bf5868d2dcbf0b28acb0501abc
Posted 5 days ago

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PD Engineer

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Job Details

Skills

Summary

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