Description Position Overview: Work closely with design teams and CAD/EDA stakeholders to identify workflow bottlenecks across the chip development lifecycle-such as DRC/CDC/STA debug, regression triage, PPA convergence, and ECO iteration. This role focuses on building scalable data pipelines and models, and integrating AI-driven solutions into production CAD and verification flows. Responsibilities: Identify and prioritize high-impact opportunities to apply AI/ML to chip design and verifica