Saratoga, California
•
Yesterday
Join a cutting-edge hardware company building next-gen silicon powering large-scale AI networking, training & inference. Were looking for a visionary Performance Modeling Leader to define and drive architectural modeling strategy that directly shapes ASIC & SoC design decisions. Lead high-level performance modeling for networking devices Partner with ASIC architects & uArch teams on PPA trade-offs Analyze throughput, latency & bottlenecks to influence architecture Build scalable modeling framew
Easy Apply
Full-time
Depends on Experience