.Validate ML-Coprocessor, display SOC, Mixed Signal SOC, and IP. Define validation strategy and test plans for new IP blocks, aligning with RTL, architecture, FW. Develop silicon validation infrastructure and coding C/C++ and Python for emulation (Zebu), FPGA (HAPS), and first silicon platforms. Identify risks and develop mitigation strategies .Execute bring-up/debug, workload enablement, and ML accelerator SW stack validation Perform performance and power characterization under real ML workload