Lead ASIC DFT Engineer

Role: Lead ASIC DFT Engineer Location: San Jose, CA (Remote, PST time zone preferred) Work Setup: Remote, PST time zone preferred Experience Required: 10+ years of hands-on experience in ASIC Design-for-Test (DFT) DFT Architecture definition. Must Full chip / Sub system level DFT activities Must Scan & compression (EDT) implementation Must LBIST implementation and verification any BIST exp is Must Coverage improvements (Spyglass work) Must ATPG Good to Have Role Summar

Position:Design For Test Engineer (IC) Job Description:What You'll Be Doing: DFT implementation for 3nm and 5nm Networking chips, IP DFT work RTL checks for scan-insertion compatibility using Synopsys Spyglass Scan-Insertion using Tessent TestKompress ATPG pattern generation: Compressed and Uncompressed Mode Tools: Mentor Tessent, Cadence Modus & Synopsys Tetramax Pattern Simulation: Without timing, With timing for different corners Tools: VCS Mismatch debug using Verdi Scripting with Perl, She

Required Skill: 5 to 8 years of Hardware verification experienceHave experience building agents, scoreboards and transactors from scratchGood knowledge of high performance microprocessor architectureUnderstanding of verification methodology Required Skills: 4 to 6 years of experienceExperience in Scan insertion with compression for Stuck-At and At-Speed test.Experience in Scan ATPG (Stuck-At and At-Speed), coverage analysis, simulation and debugExperience in MBIST insertion, simulation and debu

Company:Qualcomm Technologies, Inc. Job Area:Engineering Group, Engineering Group > CPU Engineering General Summary: As a DFT Engineer you will work with chip architects, chip designers, implementation engineers and test engineers to verify the DFT and DFD (Design for Debug) architecture, implementation, and test plans for both mixed signal and digital VLSI designs. Then you?ll insure it becomes reality. We?re doing a ground up implementation of a new chip architecture, so you?ll have to ability