DFT DV Engineer

Job Title: Lead ASIC DFT Engineer Location: San Jose, CA - Must Be Able To Go In Office Once Or Twice A Month Duration: Long term Experience Required: 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary: We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, bo

Job Description Senior Staff Engineer, Digital Verification San Jose, CA Onsite Requirements: Bachelors with 15+ years of relevant industry experience, or Masters with 13+ years or PhD with 10+ years in Electrical Engineering or related field preferred. Experience in developing test benches using SystemVerilog UVM, testcase development skills for constrained random and directed scenarios Experience in MCU/CPU Verification at processor level and at sub-system level both. a. Strong understanding

Xoriant is an equal opportunity employer. No person shall be excluded from consideration for employment because of race, ethnicity, religion, caste, gender, gender identity, sexual orientation, marital status, national origin, age, disability or veteran status. TITLE:- Sr. Staff Engineer (SystemVerilog & Digital Verification)LOCATION:- SanJose, CA (onsite)This role is part of a large RFC/RFIC/DFT engineering organization, focused on advanced digital verification across complex SoC and mixed-sig

Role: Lead ASIC DFT Engineer Location: San Jose, CA (Remote, PST time zone preferred) Work Setup: Remote, PST time zone preferred Experience Required: 10+ years of hands-on experience in ASIC Design-for-Test (DFT) DFT Architecture definition. Must Full chip / Sub system level DFT activities Must Scan & compression (EDT) implementation Must LBIST implementation and verification any BIST exp is Must Coverage improvements (Spyglass work) Must ATPG Good to Have Role Summar