Graphics FE Integration Engineer

Austin, TX, US • Posted 3 hours ago • Updated 3 hours ago
Full Time
On-site
Fitment

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Job Details

Skills

  • IPS
  • Design Analysis
  • Collaboration
  • Intellectual Property
  • IP
  • DV
  • System On A Chip
  • Verilog
  • SystemVerilog
  • Scripting
  • Perl
  • Ruby
  • Python
  • DFT
  • Management
  • Debugging
  • Logic Synthesis
  • RTL
  • Optimization
  • LEC
  • GPU
  • CPU
  • SIMD

Summary

Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you'll help design and manufacture our next-generation, high-performance, power-efficient GPU! You'll ensure Apple products and services can seamlessly and expertly handle the tasks that make them beloved by millions. Joining this group means you'll be crafting and building the technology that fuels Apple's devices. Together, we enable our customers to do all the things they love with their devices. As a member of GPU FE Design integration team, you will create GPU RTL by integrating various IPs following architectural parameters, physical constraints, DFT logic and power intent.

As a GPU Design Integration Engineer, you will be responsible for:\n\n- RTL integration, partitioning, design analysis, qualification, packaging and delivery.\n- Run logic equivalence checking between designs.\n- Ensure implementation readiness with RTL lint, custom checks and unit level synthesis.\n- Develop innovative methods to improve front-end design integration process.\n- Understand and contribute to specifications for design units.\n- Collaborate effectively with Architecture, IP, DV, SOC, DFT, IMPL teams spanning multiple sites.

BS + 3 years of relevant experience.\nExperience with Verilog/System Verilog.\nExperience with the one of the following scripting languages: Perl/Ruby/Python.

Knowledge of PPA optimization techniques and implementation flows.\nExperience with scalable designs, DFT insertion, LEC, Lint and codeline management.\nAbility to debug and solve various design integration issues in a timely manner.\nProficiency in logic design principles.\nProficiency in programming techniques.\nExperience with RTL analysis and/or PPA optimization using Invio, LEC and Genus.\nFamiliarity with GPU/CPU/SIMD Architecture and micro-architecture.\nAbility to solve complex problems across multiple technical domains.\nAbility to work well in a team and be productive under aggressive schedules.
Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.
  • Dice Id: 90733111
  • Position Id: 17c03dce685096f54199bc5227afbf63
  • Posted 3 hours ago
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