Senior Physical Design Signoff Engineer

Hi, Job Title: Physical Design Engineer Location: Cupertino, CA Work Mode: 100% Onsite (5 Days/Week) Experience: 5 15Years Job Description We are actively hiring experienced Physical Design Engineers for a leading semiconductor client in Cupertino, CA. Candidates should possess strong expertise in end-to-end physical implementation and signoff flows for advanced node SoC designs. Responsibilities Execute complete physical design implementation flow including Floorplanning, Power Planning, Pla

Job Title : Senior DFT Engineer Location : Santa Clara, CA Experience : 4+ Years in DFT Skill: [ATPG , MBIST, IO Test, Clock Verification] Job Summary We are seeking an experienced Senior DFT / ATPG Engineer to support highperformance GPU and SoC designs. The role focuses on delivering robust Design for Testability (DFT) solutions, comprehensive ATPG, and advanced test features such as MBIST, IO Test, and Clock Verification, ensuring high coverage, yield, and silicon reliability. The enginee

JobTitle:SeniorDFTEngineer[ATPG,MBIST,IOTest,ClockVerification] Location:SantaClara,CA Experience:4+YearsinDFT JobSummary WeareseekinganexperiencedSeniorDFT/ATPGEngineertosupportNVIDIAshighperformanceGPUandSoCdesigns.TherolefocusesondeliveringrobustDesignforTestability(DFT)solutions,comprehensiveATPG,andadvancedtestfeaturessuchasMBIST,IOTest,andClockVerification,ensuringhighcoverage,yield,andsiliconreliability.TheengineerwillworkcloselywithNVIDIAscrossfunctionalteamstoenablefirsttimerightsilico

Position - Signal Integrity Engineer Location - San Jose, USClient: Direct Client We have an urgent opening for a Signal Integrity Engineer to work on next-gen Security and Enterprise Routing systems. Key ResponsibilitiesDesign & analyze high-speed digital/analog systemsPerform signal integrity (SI) simulations and PCB (pre/post-layout) analysisWork on power delivery networks (PDN) / power integritySupport prototype bring-up, validation & troubleshootingCollaborate with hardware, layout & valida