ASIC Verification (Onsite In Bay area )

Location:REMOTEDuration: ~12 months (Immediate start through Q1 next year)Team Size: ~10 Engineers (Mix ofDesign & DV )Question from hiring manager on prior submital: Can you also check with the candidates on their recent hands-on experience with RTL design using SystemVerilog, & working on IPs with multiple clock domains?1. RTLDesignEngineerKey ResponsibilitiesOwn micro-architecture definition from high-level functional specificationsDevelop and implement RTL for complex digital blocksDrive dig

We are seeking a Senior / Principal Verification Engineer to lead verification architecture and execution for a next-generation scale-up switch ASIC (~500mm , TSMC 3nm/2nm). This role is critical to ensuring first-pass silicon success for a high-bandwidth, low-latency interconnect targeting AI and HPC systems. Key Responsibilities - Define full-chip and subsystem verification strategy - Architect scalable UVM environments - Develop SystemVerilog/UVM testbenches - Define and drive coverage closu

We are seeking a Senior / Principal ASIC Designer to lead micro-architecture and RTL implementation for a high-performance scale-up switch ASIC. This role focuses on translating architecture into high-quality RTL optimized for advanced nodes. Key Responsibilities - Define micro-architecture for key blocks - Develop RTL using SystemVerilog and Verilog - Optimize for power, performance, and area - Implement high-speed datapaths and pipelines - Work with physical design for timing closure - Supp