ASIC Implementation Engineer STA

Company: Qualcomm Atheros, Inc. Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: Qualcomm-Atheros, a.k.a. QCA is a wholly owned subsidiary of Qualcomm and a leading provider of wireless technologies for the mobile, networking, computing and consumer electronics markets. As a key member of a fast-paced Integrated Wireless Technology team. The role involves ownership and leading Static timing closure and synthesis for complex low-power WiFi SoCs and sub-syste

Job Description Static Timing Analysis (STA) / Timing Signoff Engineer Position Static Timing Analysis (STA) / Timing Closure & Signoff Engineer Function Physical Design Timing Signoff Experience 3 8 years of relevant STA / physical design experience Engagement Engineering services for a leading global SoC (System-on-Chip) manufacturer Location San Diego/Santa Clara or Austin (or client site as applicable) Education B.E. / B.Tech. / M.E. / M.Tech. in ECE / / VLSI / Microelectronics or equival

Position: Static Timing Analysis Engineer Location - San Jose, CA, USA What You will Do: Develop and validate timing constraints for intricate SoC designs. Expertise in Synthesis, Equivalency Checking and STA Must have Block Level and Multi-voltage Timing Closure experience. Top Level Timing Closure experience a plus. Experience with Synopsys Tools Synopsys DC/FC for Synthesis, Synopsys Formality for Equivalency Checking and Synopsys PrimeTime for STA Define and implement timing signoff method

Hiring: ASIC Physical Design Engineer Location: San Jose, CA(onsite) Experience: 7 to 12 years This requirement is similar to Physical Design Requirement (PD Engineer).Job Responsibilities: Execute synthesis, PNR, and STA for assigned partitions of ASIC chip adhering to strict schedules and design goals. Work closely with architects, RTL designers, and DFT engineers to resolve implementation and signoff issues across your blocks.Help close EM/IR, drive LEC and physical verification signoff for y