Field-Programmable Gate Arrays Engineer

Position: FPGA Verification Engineer Location: San Jose, CA - Onsite Job Description & Responsibilities Own verification of entire FPGA design used in high-end router productsUnderstand design specifications and interact with design engineers to identify verification scenariosCreate test plans, constrained-random verification environments, test cases, regressions, and coverage reportsIdentify and write all types of coverage measures for stimulus and corner-casesQualifications Strong academic ba

Job Title: FPGA Verification Engineer Location: Hybrid (4 days at Cisco SJ office and 1 day remote) Duration: 12 months Rounds of interview: There will be a total of 2 rounds: 1 screening, the second will be in-depth with 2 engineers" Job Description Own verification of entire FPGA design used in high-end router products. Understand design specifications and interact with design engineers to identify verification scenarios. Create test plans, constrained-random verification environments, t

ResponsibilitiesOwn verification of entire FPGA design used in high-end router productsUnderstand design specifications and interact with design engineers to identify verification scenariosCreate test plans, constrained-random verification environments, test cases, regressions, and coverage reportsIdentify and write all types of coverage measures for stimulus and corner-casesQualificationsStrong academic background in Electrical Engineering (Bachelors required, Masters preferred)710 years of pur

T+S Need LinkedinOnsite role. Local only Job Overview The selected engineer will: Own verification efforts for the full FPGA design used in highend router productsInterpret design specifications and collaborate closely with design engineers to define verification scenariosCreate test plans, develop constrainedrandom verification environments, and generate test cases, regressions, and coverage reportsImplement coverage measures for stimulus and cornercase scenariosDevelop objectoriented testbench