ASIC Physical Design Engineer

Company:Qualcomm Technologies, Inc. Job Area:Engineering Group, Engineering Group > CPU Engineering General Summary: As a DFT Engineer you will work with chip architects, chip designers, implementation engineers and test engineers to verify the DFT and DFD (Design for Debug) architecture, implementation, and test plans for both mixed signal and digital VLSI designs. Then you?ll insure it becomes reality. We?re doing a ground up implementation of a new chip architecture, so you?ll have to ability

Looking for an Innovative Staff Full-Chip Timing (STA) Engineer - On Site This Jobot Job is hosted by: Lindsey Cusic Are you a fit? Easy Apply now by clicking the "Apply Now" button and sending us your resume. Salary: $175,000 - $235,000 per year A bit about us: We are a growing semiconductor design organization focused on advanced ASIC and SoC development. Our team is built around deep technical expertise, fast execution, and a strong ownership mindset. We work on complex, high-performance

Job Title: DFT Engineer (6+ Years) Location: Santa Clara, California, USA Employment Type: Full-Time Job Summary We are seeking a highly skilled and motivated DFT Engineer with 6+ years of experience to join our team in Santa Clara, CA. The ideal candidate will have strong expertise in Design for Testability (DFT) methodologies, test insertion, and validation for complex SoCs. You will work closely with design, verification, and product engineering teams to ensure high-quality, testable silicon

Title: Systems Design Engineer - Emulation and Prototyping - Hybrid Mandatory skills: hardware design, FPGA Design, Synopsys HAPS, Zebu, Protium, Palladium, FPGA, emulation platforms, RTL Design, Verilog, System Verilog, Emulation Platform, Prototyping Platform, SoC designs, RTL coding, AXI, ACE, APB, PCIe, DDR, Ethernet, SerDes links, debugging tools, RTL, Verdi, fsdb analysis, ASIC design flows, emulation, scripting, automation, Python, Perl, Tcl, Make, CMake, Shell, RTL patches, model creatio