Verification Engineer

Strong System Verilog & UVM experienceDigital design/RTL verification expertiseExperience with verification methodologies/tools (formal verification, coverage, simulation, scripting)Familiarity with AXI protocolFamiliarity with UCIe would be a nice-to-have

RequirementsKnowledge of semiconductor ASIC design/verification methodologies and flows Working knowledge of Verilog/SystemVerilog/UVM Strong programming skills including object-oriented programming Working experience with digital logic design and verification Practical experience in D2D, NOC, AXI, Ethernet, DDR/LPDDR, HBM, Security, Networking, ARM CPU subsystems Demonstrates good analysis, problem-solving, and critical thinking skills Effective interpersonal, teamwork, and communication skills

Our client seeks an Senior Validation Engineer for a 12 Months project in San Diego, CA . Below is the detailed requirement Title: Senior Validation Engineer (Oracle SCM) Location : San Diego, CA (Remote) Duration:12 Months - UK Shift Time Job Description: Bachelor's degree preferably in Computer Science, Information technology, Computer Engineering, or related IT discipline or equivalent experience with 12+ Minimum Experience validation is must skills to support NetSuite Validation Eng

5+ years of digital front-end / RTL design experienceExperience integrating CPU cores, bus architectures, and peripheral IPs into SoC or ASIC designsWorking knowledge of ARM AMBA protocols AXI / AHB / APB(Assumption: viewed as a strong plus please let me know if this should be mandatory) Strong subsystem-level integration and debug skillsProficiency in Verilog / SystemVerilog