DFT Engineer

Role :- Senior ASIC DFT CDC Constraints Eng Location :- San Jose, CA/Milpitas, CA (Remote) Type :- */W2 This is a highly specialised role at the intersection of Design for Test (DFT) architecture and clock domain crossing (CDC) constraint engineering. The successful candidate will own the SDC/SSTA constraint strategy that governs both functional timing closure and DFT scan-mode operation across a complex multi-clock SoC. You will work daily at the boundary where CDC violations manifest as sca

Familiarity with the Siemens suite of DFT toolsDFT insertion for SCAN (with SSN) and MBISTMBIST Repair Implementation and VerificationGenerating collaterals for Test Timing and Place and RouteExpertise in IJTAG 1687 standard and good at understanding ICL and PDL standard SpecVerification of DFT features, includingBoundary ScanJTAGSCANMBISTHigh Speed IO

Hi, Job Title : Senior DFT Engineer [ATPG , MBIST, IO Test, Clock Verification] Location : Santa Clara, CA Experience : 4+ Years in DFT Job Summary We are seeking an experienced Senior DFT / ATPG Engineer to support client s highperformance GPU and SoC designs. The role focuses on delivering robust Design for Testability (DFT) solutions, comprehensive ATPG, and advanced test features such as MBIST, IO Test, and Clock Verification, ensuring high coverage, yield, and silicon reliability. The engin

Job Title: DFT / ATPG Engineer Location:Santa Clara, CA (Onsite) Duration: 12+ Months Job Summary We are seeking an experienced Senior DFT / ATPG Engineer to support highperformance GPU and SoC designs. The role focuses on delivering robust Design for Testability (DFT) solutions, comprehensive ATPG, and advanced test features such as MBIST, IO Test, and Clock Verification, ensuring high coverage, yield, and silicon reliability. The engineer will work closely with crossfunctional teams to enab