Design Verification Engineer - San Jose, CA – Onsite - Contract Role

San Jose, CA, US • Posted 3 hours ago • Updated 3 hours ago
Contract Corp To Corp
Contract Independent
Contract W2
12 Months
No Travel Required
On-site
Depends on Experience
Fitment

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Job Details

Skills

  • subsystems: PCIe
  • Ethernet
  • CPU (arc/arm)
  • low power peripherals
  • sensors

Summary

Job description:

 

We are seeking a Design Verification Engineer to join our Interface IP DV team.

You will work with architects, designers, and vendors to ensure that all our architecture requirements are met in the IP subsystems and interfaces being created, validate correctness and performance across the full hardware-software stack.

This role demands creativity, deep technical ability, and the drive to tackle complex verification challenges.

 

Key responsibilities

  1. End to end ownership of one or more of the following IP subsystems: PCIe, Ethernet, CPU (arc/arm), low power peripherals, sensors
  2. Understand vendor IP configurations and handle handshake with internal IP team
  3. Develop and maintain UVM/SystemVerilog-based verification environments to ensure functional correctness, performance, and compliance with IP specifications.
  4. Collaborate with integration and SoC DV teams to validate seamless interaction of external IPs within the broader chip architecture.
  5. Drive coverage closure and sign-off by defining metrics, analyzing gaps, and ensuring comprehensive verification across corner cases and stress scenarios.
Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.
  • Dice Id: 10120137
  • Position Id: 69294-10367-
  • Posted 3 hours ago
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