Contract Hardware Engineer Mid/ Design Verification Engineer

Do something big and innovative! Stretch your creative muscles and work on big issues. Since 1989, we have developed technology environments, applications, and tools by providing experienced teams to implement, enhance, and maintain our clients essential systems and applications. Join our team and be part of developing a reference design for our next gen of glasses. Required Skills & Qualifications:Bachelors or Masters in Electrical Engineering and/or Computer Science with a minimum of 3 years

Job Title:Hardware Testing Engineer # of Roles: Multiple Roles Location:Santa Clara, Ca (Onsite daily) Duration:5 months Shift Notes: Must be will to work OT and weekends as necessary What you'll be doing: Assemble, build, and install bench top development platforms and large server systems.Prepare boards for detailed solder reworks to be completed by another lab.Connect oscilloscope probes to boards and collect signal waveform data.Perform mechanical reworks involving power tools such as a Drem

Quick feedback One to two interview process Microsoft Teams MUSTbe able to work onsite inSanta Clara no exceptions Key points: UVM Systemverilog 10+ years of exp Onsite in Santa Clara 1 year We are looking forstrong SoC DVcandidates to work onsite in San Jose. System-level experience is highly preferred. Familiarity withAXI4 is preferred Strong SystemVerilog and UVM skillsScripting experience (Python/Perl/Shell) is a plusC-based programming experience is a strongplusExperience with infrastru

Xoriant is an equal opportunity employer. No person shall be excluded from consideration for employment because of race, ethnicity, religion, caste, gender, gender identity, sexual orientation, marital status, national origin, age, disability or veteran status. TITLE:- Sr. Staff Engineer (SystemVerilog & Digital Verification)LOCATION:- SanJose, CA (onsite)This role is part of a large RFC/RFIC/DFT engineering organization, focused on advanced digital verification across complex SoC and mixed-sig