PCB Layout Engineer (High-Speed Server Board Design)

Location: Bay Area, CA (Onsite)
Duration: 6+ Months (Contract)

Job Summary

We are seeking an experienced PCB Layout Engineer with strong expertise in high-speed PCB layout and server board design. The ideal candidate will have hands-on experience designing complex multilayer server boards and be highly proficient in Cadence Allegro PCB Designer version 22.1 or higher. This role requires close collaboration with hardware, signal integrity, power integrity, and mechanical engineering teams to deliver high-performance server and data center hardware designs.

Key Responsibilities

• Design and develop high-speed PCB layouts for complex multilayer server boards.
• Create PCB layouts for high-density designs involving DDR4/DDR5, PCIe Gen4/Gen5, Ethernet, USB, SATA, NVMe, and other high-speed interfaces.
• Perform component placement, routing, stack-up planning, impedance control, and design optimization.
• Work closely with hardware design engineers, SI/PI engineers, and manufacturing teams throughout the design cycle.
• Ensure PCB designs meet signal integrity, power integrity, EMI/EMC, thermal, and manufacturability requirements.
• Generate and validate manufacturing outputs including Gerber, ODB++, fabrication, and assembly documentation.
• Support design reviews, engineering change orders (ECOs), prototype bring-up, and production readiness.
• Collaborate with PCB fabrication and assembly vendors to resolve design and manufacturing issues.

Required Qualifications

• Bachelor’s degree in Electrical Engineering, Electronics Engineering, or a related field.
• 5+ years of PCB layout experience, with significant experience in high-speed server board design.
• Strong hands-on expertise with Cadence Allegro PCB Designer v22.1 or higher.
• Experience designing multilayer HDI PCBs with controlled impedance and high-speed routing.
• Strong understanding of:
  • DDR4/DDR5 memory routing
  • PCIe Gen4/Gen5
  • High-speed differential pair routing
  • Length matching and timing constraints
  • Power distribution networks
  • EMI/EMC and design for manufacturability (DFM/DFA)
• Experience with server, storage, networking, or data center hardware platforms.
• Ability to interpret schematics and collaborate effectively with cross-functional engineering teams.

Preferred Qualifications

• Experience with SI/PI constraints implementation.
• Familiarity with Allegro Constraint Manager and advanced routing automation features.
• Experience supporting prototype validation and manufacturing builds.
• Knowledge of thermal considerations and mechanical integration for server platforms.
• Exposure to design collaboration tools such as PLM, ECAD-MCAD integration, and revision control systems.

Key Skills

• High-Speed PCB Layout
• Server Board Design
• Cadence Allegro PCB Designer 22.1+
• DDR4/DDR5
• PCIe Gen4/Gen5
• Multilayer PCB Design
• HDI PCB Layout
• Signal Integrity (SI)
• Power Integrity (PI)
• Impedance Control
• Differential Pair Routing
• DFM / DFA
• PCB Manufacturing Documentation
• ECO and Prototype Support