SoC Failure Analysis Engineering Program Manager

Apple's Engineering Program Management (EPM) team is seeking a seasoned Senior Engineering Program Manager to join and drive the SoC Failure Analysis (FA) efforts. \\n\\nIn this role, you will be the driving force behind the operational excellence and program execution of FA across Apple's silicon lifecycle. You will own process definition, sample and logistics flow, cross-site coordination, and institutional knowledge capture - while actively partnering with technical leads on debug engagements to move issues from failure signature to resolution with speed and rigor. Serving as the critical link between high-level system failures and IP/circuit-level voltage and performance limitations, you will coordinate efforts across design, validation, and Apple FA labs, directly supporting the engineers building the chips at the core of future Apple products loved by millions of customers.

Drive Technical Debug: Actively participate in bench-level functional debug on silicon validation boards and sockets, driving programs from failure signature through root-cause identification, and coordinate advanced EFA techniques (Sample Prep, EMMI, LVP, DLS, Nano-Probing, FIB) to isolate faults across analog, mixed-signal, and digital ICs.\n\nEstablish Processes and Workflows: Define, document, and continuously improve FA intake, triage, prioritization, escalation, and closure workflows across Austin and Cupertino labs, and lead initiatives that measurably reduce turnaround time and increase FA throughput.\n\nOrchestrate Cross-Functional Execution: Partner closely with Design, Product Engineering, DFT, Reliability, Validation, and Foundry teams to drive measurable improvements in performance and yield, aligned to product launch milestones, while serving as the connective tissue between Austin and Cupertino FA labs.\n\nInstitutionalize Learnings: Build and maintain the FA knowledge base - failure signature libraries, debug playbooks, and lessons-learned repositories - and facilitate structured retrospectives that drive a culture of continuous learning across silicon generations.\n\nOwn Logistics and Operational Reporting: Manage sample lifecycle logistics, EFA tool scheduling, and cross-site/vendor coordination, and define KPIs (TAT, throughput, tool utilization) to drive operational reviews, capacity planning, and capex prioritization with lab managers.

BS + 10 years of relevant experience.\nStrong semiconductor industry background with a career progression from hands-on technical roles (Failure Analysis, Silicon Debug, Silicon Validation, or Product Engineering) into program/project management, with 10+ years of combined experience and demonstrated ownership of FA or debug programs.\nWorking familiarity with bench-level electrical verification and fault isolation, and the ability to coordinate across FA techniques for specific fault types (high leakage, open/short, high resistance, weak transistors) at a program-driver level.\nWorking knowledge of VLSI circuit design, manufacturing, packaging, and chip validation processes for 5nm technology and below.

Advanced Experience: 15+ years spanning technical and program management roles in design debug, product development, SoC functional verification, and advanced failure analysis.\nTechnical Depth: Hands-on or management-level familiarity with EMMI, LVP, DLS, Nano-Probing, and FIB for fault isolation, with exposure to SoC functional verification, characterization, sample prep, advanced wafer-level packaging, and PD/STA concepts sufficient to support post-silicon data discussions.\nOperational Excellence: Track record of implementing knowledge management systems or engineering playbooks at scale, with measurable improvements in TAT, throughput, or yield through process redesign.