Opening for FPGA Verification Engineer in Mountain View, CA-Hybrid || Contract

Hi, our client is looking for a FPGA Verification Engineer. Role:: FPGA Verification Engineer Location: Mountain View, CA Visa: Any valid working visa Type: Hybrid Job Description Strong understanding of FPGA design principles and architectures. Proficiency in System Verilog and UVM verification methodology. Experience with industry-standard verification tools (e.g., QuestaSim, Synopsys VCS). Knowledge of code coverage and functional coverage analysis. Excellent debugging and problem-solving

Job Title : FPGA Verification Engineer Santa Clara, CA- 5 days onsite Hire Type: Contract Job Description: We are seeking a highly motivated and skilled FPGA Verification Engineer to join our dynamic team. In this role, you will be responsible for the verification of complex FPGA designs, ensuring their functionality, performance, and reliability. You will work closely with design engineers to develop and execute verification plans, identify and debug issues, and contribute to the overall qualit

Job Title: "Design Verification Engineer (GPU)" Location: San Jose, CA (Onsite, 5 days a week) Duration: Long Term Description As a GPU Design Verification Engineer, your talents will ensure the quality at the heart of our GPU architecture. Creativity is a necessity to overcome the challenges inherent to verifying the proper operation of our low-power GPU. Versatility and broad knowledge of state-of-the-art verification techniques including the most up-to-date I UVM version will place you among

Job Title: FPGA Verification Engineer Location: Hybrid (4 days at Cisco SJ office and 1 day remote) Duration: 12 months Rounds of interview: There will be a total of 2 rounds: 1 screening, the second will be in-depth with 2 engineers Job Description Own verification of entire FPGA design used in high-end router products. Understand design specifications and interact with design engineers to identify verification scenarios. Create test plans, constrained-random verification environments, te