1 - 15 of 15 Jobs

Sr Specialist, Electrical Engineering - VHDL/FPGA Engineer

L3Harris Technologies

Mason, Ohio, USA

Full-time

Job Title: Sr Specialist, Electrical Engineering - VHDL/FPGA Engineer Job Code: 9420 Job Location: Mason, Ohio or Hybrid Schedule: 9/80 Schedule Sr Specialist, Electrical Engineering (VHDL/FPGA Engineer) About Space & Sensors: L3Harris Space & Sensors Division, headquartered in Mason, Ohio, designs, develops, and manufactures complex systems (electronic, avionics, transceivers, transmitters, electro-optical, and electro-mechanical) for the defense, aerospace, and commercial markets. L3Harr

RTL Design Engineer - Onsite

VIVA USA INC

Santa Clara, California, USA

Contract

Title: RTL Design Engineer - Onsite Description: JOB DUTIES: Responsible for RTL design using Verilog HDL for implementation and debug. Read and comprehend System on Chip level architectural specification. Write microarchitecture specification for new and modified functions. Responsible for linting and simulation of design. Work with synthesis and backend teams for physical implementation. EDUCATION: Bachelor's or Master's in Computer Engineering KEY RESPONSIBILITIES: Perform RTL design of di

FPGA Electrical Engineer - G

Next Step Systems

Linthicum Heights, Maryland, USA

Full-time

FPGA Electrical Engineer, Linthicum Heights, MD We are looking for multiple candidates at multiple levels for this position. All candidates must be fully vaccinated with an FDA authorized and/or approved COVID-19 vaccine as a condition of employment. Requests for reasonable accommodation for medical, religious, or other reasons will be considered in accordance with applicable law. These positions are 100% Onsite. FPGA Electrical Engineer Responsibilities: - Participate in all phases of FPGA de

Senior FPGA Electrical Engineer - G

Next Step Systems

Linthicum Heights, Maryland, USA

Full-time

Senior FPGA Electrical Engineer, Linthicum Heights, MD We are looking for multiple candidates at multiple levels for this position. All candidates must be fully vaccinated with an FDA authorized and/or approved COVID-19 vaccine as a condition of employment. Requests for reasonable accommodation for medical, religious, or other reasons will be considered in accordance with applicable law. These positions are 100% Onsite. Senior FPGA Electrical Engineer Responsibilities: - Participate in all pha

Principal Digital Design Engineer, SoC

Island Staffing

San Jose, California, USA

Full-time

As a Principal Engineer/Manager, Digital Design SoC, you will be leading with a small team of design engineers to develop novel SoC products for connectivity and communications. You will also be a key contributor to product definition and resulting detailed device performance and functional requirements specifications. You will support other discipline teams to bring the SoC device to successful mass production. This full-time position is based in San Jose, CA. Key Responsibilities Review and co

IO Subsystem Architect

Qualcomm Technologies

San Diego, California, USA

Full-time

Company:Qualcomm Technologies, Inc. Job Area:Engineering Group, Engineering Group > ASICS Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. The infrastructure IP Team consists of a multi-disciplinary group involved in the definition and design of Platform infrastructure HW component

Digital Design Engineer

Qualcomm Technologies

San Diego, California, USA

Full-time

Company:Qualcomm Technologies, Inc. Job Area:Engineering Group, Engineering Group > ASICS Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (bl

Sr. RTL Design Engineer

Infobahn Softworld Inc.

Santa Clara, California, USA

Third Party, Contract

Location: San Jose, CA - Hybrid (at least 3 days a week) KEY RESPONSIBILITIES: Microarchitecture development of IP subsystems Perform RTL design of digital components. Work with functional verification team to meet coverage and quality standards. Analyze/fix Lint and CDC errors of the components. Guarantee quality/timely deliverables meeting project's schedule. Help to improve/automate design process. Support post-silicon product bring-up/debug. PREFERRED EXPERIENCE: 10 years' experience in RTL

Sr. Coherent Designer

Xoriant Corporation

Austin, Texas, USA

Contract

Job Title: Sr. Coherent Designer Location: Austin Texas Duration: 6+ Months (possible extension + long term project) Description As a senior designer on coherent interconnect micro-architect, you will be responsible for working on the micro-architecture development of custom coherent interconnect IP and/or last level cache blocks.In this role you will be interacting with the system architects, verification, performance/power and design implementation teams.You will be owning and driving the crit

GPU Power Engineer

Qualcomm Technologies

San Diego, California, USA

Full-time

Company:Qualcomm Technologies, Inc. Job Area:Engineering Group, Engineering Group > GPU ASICS Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm GPU Engineer, you may architect, design, implement, verify, and/or optimize the performance and power of GPU cores. Qualcomm Engineers collaborate with

RTL Design Engineer

Xoriant Corporation

San Jose, California, USA

Contract

Title: RTL Engineer Location: San Jose, CA | San Diego, CA | Austin Texas Duration: 6+ months (Possible Extension-Long Term Project) Job Description As a senior RTL design engineer, you will work as part of a memory controller IP design team.You will be tasked with driving the RTL design, performance and power optimization of various sub-blocks of the dynamic memory controller.Solid engineer foundation and RTL design experience is desired for success.Key responsibilities include: Produce quality

RTL/ASIC Design Engineer

Netwoven

San Jose, California, USA

Contract

KEY RESPONSIBILITIES: Microarchitecture development of IP subsystems Perform RTL design of digital components. Work with functional verification team to meet coverage and quality standards. Analyze/fix Lint and CDC errors of the components. Guarantee quality/timely deliverables meeting project s schedule. Help to improve/automate design process. Support post-silicon product bring-up/debug. PREFERRED EXPERIENCE: 10 years' experience in RTL coding Knowledge of PCIe Gen5 and PIPE specification Kno

ASIC Design Engineer

BlackFern Recruitment

Milpitas, California, USA

Full-time

Job Description Front-End ASIC Design Engineer - Milpitas, CA Our client develops and delivers ASIC and SoC solutions to customers worldwide in some of the hottest technology areas. The Front-End ASIC Design Engineer will be a key person in this growing design department. Micro-architecture experience is required. Great opportunity to work on current, ongoing and upcoming new projects. Hybrid remote/onsite position. Primary responsibilities include: Support customer s design through all phases o

ASIC/SoC Design Verification Engineer

TetraMem Inc

Fremont, California, USA

Full-time

Responsibilities: Collaborate with design engineers and architects to define, document and implement detailed test plans for the SoC design verification. Build and maintain infrastructure/environment for automation verification of SoC architecture, function and performance. Develop reusable testbench, constrained-random/directed testcases, and verification associated behavioral module for both of block levels and system levels. Develop regression strategy, methodology and tools(scripts). Define

ASIC RTL / SoC Design Engineer

TetraMem Inc

Fremont, California, USA

Full-time

Responsibilities: Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring robust and efficient designs. Integrate and validate IP blocks within the larger system, ensuring seamless functionality and compatibility. Thoroughly comprehend both internal and external requirements, conducting Power, Performance, and Area (PPA) analysis to optimize design trade-offs. Collaborate closely with the backend team, participating in RTL coding, implementation, and synthe