ASIC jobs in California

ASIC/SOC DFT Engineer (Silicon Engineering)

Palo Alto, California

•

Today

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. ASIC/SOC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world's

Full-time

USD 135,000.00 - 175,000.00 per year

FPGA/ASIC Design Engineer (Silicon Engineering)

Irvine, California

•

Today

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. FPGA/ASIC DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the worl

Full-time

Compensation information provided in the description

ASIC Validation Lead/Engineering Manager

Sunnyvale, California

•

Today

Qualifications 10+ years of experience in software development, validation, and software delivery management, including managed services team leadership.8+ years of experience in silicon validation, test engineering, or hardware infrastructure, with 3+ years in engineering management.Deep understanding of ASIC validation methodologies, including PVT characterization, frequency binning, power/thermal analysis, and production test flows.Experience building and operating CI/CD pipelines for hardwar

Easy Apply

Contract

Depends on Experience

Lead ASIC DFT Staff Engineer

Remote

•

Today

Job Description: Key Skills : "SCAN, ATPG, MBIST, Timing Simulations, SDF, SDC , PSV, Diagnosys , Pattern Retargeting , Pattern porting, DRCs, TetraMax, DFTMax " Experience: 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary: We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertio

Contract

USD70.0/HOURLY - USD80.0/HOURLY

Principal ASIC Verification Engineer

San Jose, California

•

Today

Principal ASIC Verification Engineer San Jose, CA 6 + Months $95 - $100/HR Role: Lead block-level functional verification for complex CPU/GPU SoCs using directed and constrained-random testing. Must Have: 10+ years experience, expert C/C++ in Linux environments, OOP/STL, debug tools (Gdb/Valgrind), and Verilog/SystemVerilog. Dexian stands at the forefront of Talent + Technology solutions with a presence spanning more than 70 locations worldwide and a team exceeding 10,000 professionals. As one

Easy Apply

Contract

$95 - $100 per hour

ASIC Verification Engineer

Santa Clara, California

•

Today

ASIC Verification Engineer Santa Clara, CA 12 + Months $75 - $80/HR Role: Lead block-level functional verification for complex CPU/GPU SoCs using directed and constrained-random simulation. Must Have: 5-7 years experience, expert C/C++ in Linux, OOP/STL, and Verilog/SystemVerilog (Formal Verification / 7+ years preferred). Dexian stands at the forefront of Talent + Technology solutions with a presence spanning more than 70 locations worldwide and a team exceeding 10,000 professionals. As one o

Easy Apply

Contract

$75 - $80 per hour

VLSI Physical Design Engineer - ASIC/SoC - RTL to GDS (10+ Yrs)

Folsom, California

•

Today

VLSI Physical Design Engineer - ASIC/SoC - RTL to GDS Folsom, CA 3 + Months Role: Lead block-level physical design from RTL to GDSII. Must Have: 10+ years exp, advanced nodes, and Fusion Compiler. Dexian stands at the forefront of Talent + Technology solutions with a presence spanning more than 70 locations worldwide and a team exceeding 10,000 professionals. As one of the largest technology and professional staffing companies and one of the largest minority-owned staffing companies in the Un

Easy Apply

Contract, Third Party

$90 - $100 per hour

ASIC Engineering Technical Leader

San Jose, California

•

Today

Role: ASIC Engineering Technical Leader Location: San Jose, CA (Onsite) Start Date: Immediate Type: Contract (C2C/W2) Interview: Phone/Video We are seeking an ASIC Engineering Technical Leader with strong expertise in DesignforTest (DFT) for nextgen optical communication ASICs. Responsibilities include DFT architecture implementation, scan insertion, ATPG pattern generation, silicon debug, integration/verification of DFT fabrics, gatelevel simulations, and automation using Python/Tcl/C++.

Easy Apply

Full-time, Part-time, Third Party, Contract

ASIC Design Engineer

Mountain View, California

•

Today

Hi , This role is a Full Time / Permanent . Title: Senior ASIC / SoC Network-on-Chip Design Engineer or Senior ASIC Design Engineer Location : Mountain View CA Qualifications 8+ years delivering ASIC/SoC IP designs. 6+ years of hands-on digital design, RTL, and microarchitecture experience. Strong experience with Verilog/SystemVerilog, synthesis, timing constraints, CDC, Lint, and PPA trade-offs. Experience with NoC/interconnect and high-throughput/low-latency designs. Experience with SoC

Easy Apply

Full-time

Depends on Experience

Lead ASIC DFT Staff Engineer

Remote

•

11d ago

Job Description: Key Skills : SCAN, ATPG, MBIST, Timing Simulations, SDF, SDC , PSV, Diagnosys , Pattern Retargeting , Pattern porting, DRCs, TetraMax, DFTMax Experience: 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary: We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG,

Easy Apply

Contract, Third Party

Depends on Experience

Senior DFT Engineer

Santa Clara, California

•

3d ago

Amtex Systems Inc is an information technology and talent solutions company offering talent and BI consulting to the companies in US for over 25 years. Our solutions are designed to fill resource gaps, by providing the right candidates who deliver value to the organization. Our propensity to nurture and build strong relationships with our clients helps us better understand their business demands and gives us the ability to provide services that are on time and rise above the rest. Senior DFT Eng

Easy Apply

Third Party, Contract

Depends on Experience

Lead ASIC DFT Staff Engineer at Remote

Remote

•

30+d ago

Job Title: Lead ASIC DFT Staff Engineer Location: Remote (must be aligned with PST time zone) Long Term Contract Job Description: We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug eff

Easy Apply

Contract, Third Party

90 - 100

RTL Design Engineer

California

•

Today

Job Title: Senior RTL Engineer Location: Saratoga, CA (Onsite) Duration: Full-Time Job Description: Packet buffering, queuing, and scheduling: Work on micro architecture and design implementation of high-speed networking ASIC's, focusing on latency optimization and quality of service (QoS) support. Experience with on-chip memory subsystem and scheduling / arbitration design. Implementation and Testing: Implement designs on ASIC platforms, ensuring compliance with industry standards and perform

Easy Apply

Full-time

Formal Verification

Ben Lomond, California

•

24d ago

JOB DUTIES: Participate in the functional verification of a block(s) of complex ASICs and/or IP cores for a combined CPU/GPU development effort. Be part of a team of design and verification engineers, working closely with other team members to understand and verify the functionality of a given design element within the context of the block, chip and overall system. Be responsible for carefully documenting and executing test plan(s) consisting of directed and constrained-random tests to be run du

Easy Apply

Third Party, Contract

Depends on Experience

DFT Engineers

Santa Clara, California

•

8d ago

5+ years of hands-on experience in DFT and ATPG for SoC or ASIC designsStrong understanding of DFT fundamentals including controllability, observability, and scan-based testingProven expertise in ATPG pattern generation, analysis, and debugExperience with MBIST, including memory test architectures and diagnosticsKnowledge of IO Test methodologies for interface and pin level validationSolid understanding of clock DFT and clock verification conceptsStrong grasp of digital design and RTL fundamenta

Easy Apply

Contract

Depends on Experience

Physical Design Engineer (Top-Level / Full-Chip) - AS

San Jose, California

•

Yesterday

Title: Physical Design Engineer/ ASIC Implementation Engineer (Strong Top-Level / Full-Chip Physical Design and Implementation experience) Location: San Jose, CA (Onsite role) Type: FTE Permanent role Note from Hiring manager: Candidate either should have good experience on Chip level/Top level design Or if they are extremely strong in one of the other aspects of design e.g. STA (Static Timing Analysis) or Floor Planning in chip design, they can still be considered. Only in those cases where y

Easy Apply

Full-time

Depends on Experience

DFT (Design for Test) Lead

Remote

•

Yesterday

Job Title: DFT (Design for Test) Lead Location: (Remote) Shift: 9am 5pm PST Duration: 12+ Months Contract Role on W2 Job Responsibilities:Responsible for implementing the Hardware Design-for-Test (DFT) features - scan, mbist, BISR, boundary scan, setting up/debugging DFT simulations and supporting post-silicon testing/debugResponsible for development of innovative DFT IP in collaboration with the multi-functional teams, and play a key role in full chip design integration with the testability f

Easy Apply

Contract

75 - 80

DFT Engineers

Santa Clara, California

•

Today

Job Description: 5+ years of hands-on experience in DFT and ATPG for SoC or ASIC designsStrong understanding of DFT fundamentals including controllability, observability, and scan-based testingProven expertise in ATPG pattern generation, analysis, and debugExperience with MBIST, including memory test architectures and diagnosticsKnowledge of IO Test methodologies for interface and pin level validationSolid understanding of clock DFT and clock verification conceptsStrong grasp of digital design

Easy Apply

Full-time

DFT (Design For Test) Lead - Remote Role

Remote

•

2d ago

Role: ASIC DFT (Design for Test) LeadLocation: RemoteDuration: 12+ months (possibly extending longer based on project timelines)Candidate Responsibilities:Responsible for implementing the Hardware Design-for-Test (DFT) features - scan, mbist, BISR, boundary scan, setting up/debugging DFT simulations and supporting post-silicon testing/debugResponsible for development of innovative DFT IP in collaboration with the multi-functional teams, and play a key role in full chip design integration with t

Easy Apply

Contract

Depends on Experience

DFT Engineer

San Jose, California

•

9d ago

DFT EngineerIntroduction:The DFT Engineer position at Sivaltech Inc involves working on ASIC/SoC designs, implementing Design for Testability (DFT) techniques, and ensuring the efficient testing of semiconductor devices. The role requires expertise in DFT tools, verification, testing, and debugging to support the overall product development lifecycle. Responsibilities:Implement DFT strategies for ASIC/SoC designsWork on Scan, JTAG, BIST, and MBIST techniquesGenerate test patterns and verify DFT

Easy Apply

Contract, Third Party

Depends on Experience

ASIC jobs in California, USA