ASIC jobs in California

ASIC/SOC DFT Engineer (Silicon Engineering)

Palo Alto, California

•

Today

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. ASIC/SOC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world's

Full-time

USD 135,000.00 - 175,000.00 per year

Lead ASIC DFT Staff Engineer

Remote

•

Today

Job Description: Key Skills : "SCAN, ATPG, MBIST, Timing Simulations, SDF, SDC , PSV, Diagnosys , Pattern Retargeting , Pattern porting, DRCs, TetraMax, DFTMax " Experience: 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary: We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertio

Contract

USD70.0/HOURLY - USD80.0/HOURLY

ASIC/FPGA Verification Engineer III, Secret Clearance

Poway, California

•

17d ago

Job Description Join Our Team as a ASIC/FPGA Verification Engineer where you will work on the development of a sophisticated state-of-the-art avionics product in a world class Integrated Product Development environment. Location: This position does not support teleworking; the selected candidate will be located near our Lockheed Martin Space facility in: Denver CO or Highlands Ranch CO Sunnyvale CA You will work a flexible 9x80 schedule in the office full-time. What does this role look like?

Full-time

USD 101,000.00 - 178,135.00 per year

ASIC/FPGA Design Engineer III, Secret Clearance

Poway, California

•

17d ago

Job Description Join Our Team as a ASIC/FPGA Design Engineer where you will work on the development of a sophisticated state-of-the-art avionics product in a world class Integrated Product Development environment. Location: This position does not support teleworking; the selected candidate will be located near our Lockheed Martin Space facility in: Sunnyvale CA Denver CO Highlands Ranch CO You will be working a flexible 9x80 schedule in the office full-time. About Lockheed Martin Space Spac

Full-time

USD 101,000.00 - 178,135.00 per year

Digital Engineer (FPGA/ ASIC)

Los Angeles, California

•

Today

Location: Los Angeles, CA Salary: $70.00 USD Hourly - $95.00 USD Hourly Description: Job Title: Digital Engineer (FPGA/ ASIC) Duration: 1+ year (Possible extension or Perm) Location: About the Role We are looking for you to join our team as a Principal Digital Engineer based out of Woodland Hills, CA. As a Principal Digital Engineer you will have a challenging and rewarding opportunity to be a part of our Enterprise-wide digital transformation. Using Model-based Engineering, DevSecOps and Agil

Contract

Compensation information provided in the description

FPGA/VLSI engineer

California City, California

•

Yesterday

We are seeking an FPGA/VLSI engineer to contribute to digital hardware development targeting ASIC/SoC platforms used in advanced communication systems. This role focuses on RTL design, FPGA prototyping, and system integration, working closely with cross-functional teams to deliver high-quality designs. Responsibilities: Design and implement RTL using SystemVerilog with consideration for timing, power, and area Perform FPGA prototyping, validation, and hardware bring-up for digital designs Develo

Easy Apply

Full-time

Depends on Experience

Remote (PST time zone preferred) -- Lead ASIC DFT Engineer

San Jose, California

•

29d ago

Hello Professional, Good Afternoon Please find the job description give below, if interested please share me your most updated copy of resume. Role: Lead ASIC DFT Engineer Work Setup: Remote, PST time zone preferred Experience Required:10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary: We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep tec

Easy Apply

Contract, Third Party

Depends on Experience

Lead ASIC DFT Staff Engineer

Remote

•

Today

Job Description: Key Skills : SCAN, ATPG, MBIST, Timing Simulations, SDF, SDC , PSV, Diagnosys , Pattern Retargeting , Pattern porting, DRCs, TetraMax, DFTMax Experience: 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary: We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, M

Easy Apply

Contract, Third Party

80 - 90

RTL Engineer, Networking ASIC

Saratoga, California

•

7d ago

Qualifications ME/BE with a minimum of 8-15 years of experience.Hands-on knowledge of SystemVerilog and Verilog is mandatory.Solid understanding of ASIC design methodologies, including simulation, verification, synthesis, and timing adjustments.Proven expertise in designing and optimizing scheduling and QoS mechanisms.Experience with Ethernet and IP protocols.Strong analytical and problem-solving abilities, with meticulous attention to detail in troubleshooting and debugging complex networking i

Easy Apply

Full-time

200000 - 220000

Business Development – Semiconductor / ASIC

Remote

•

6d ago

Business Development Engineer Semiconductor / ASICJob DescriptionWe are seeking an experienced Business Development professional to support the growth of custom and standard semiconductor products. The ideal candidate will combine strong business development capabilities with technical expertise in areas such as Design Automation, FPGA, ASIC Design, or semiconductor packaging. This position will support customers across the military/aerospace, industrial, and medical markets, working closely wi

Easy Apply

Full-time

140,000 - 180,000

ASIC Emulation Engineer

San Jose, California

•

29d ago

Key Skills:Veloce, Palladium, or ZeBu, PCIe and UCIe and memory technologies such as LPDDR and HBM Set up and maintain Siemens Veloce emulation and prototyping platforms Adapt SoC designs for Emulation and Prototyping Develop and debug emulation testbenches and system-level environments Support pre-silicon validation, power/performance analysis, and early software bring-up. Participate in silicon bring-up and validation. Collaborate with design and verification teams to isolate design issues and

Easy Apply

Contract

60 - 75

Lead ASIC DFT Staff Engineer

Remote

•

Yesterday

Easy Apply

Third Party, Contract

Depends on Experience

Technical Leader Network SDK QA | Saratoga, CA

Saratoga, California

•

8d ago

We are seeking a hands-on Technical Leader Network SDK QA to lead the quality strategy for next-generation switching platforms. In this role, you will own SDK validation, design automated test frameworks, mentor QA engineers, and collaborate with SDK, ASIC, and Network OS teams to ensure reliable, high-performance software releases. Required Skills: 8+ years of QA/validation experience in networking SDKs, Network OS, or embedded systemsStrong knowledge of L2/L3 networking, ACLs, QoS, and multica

Easy Apply

Full-time

Depends on Experience

ASIC Manufacturing Project Architect

San Jose, California

•

12d ago

Were hiring for a full-time opportunity with a leading semiconductor R&D organization in USA. This role focuses on ASIC Manufacturing Project Architect. Detailed job description is given below. Please share your resume to Job Title: Project Architect Backend (ASIC Manufacturing / Semiconductor) Location:San Jose, CA (Onsite) Type: Full-Time | Direct Hire with End Client Experience:10+ Years Job Summary We are seeking an experienced Project Architect to lead technical customer engagement

Easy Apply

Full-time, Third Party

Depends on Experience

Senior ASIC RTL DESIGN Engineer

Remote or Hybrid in Boston, Massachusetts

•

20d ago

12 Months + CONTRACT Starting in September SKILLS: SENIOR ASIC RTL Design Verilog High Speed Memory Interface Experience Logic synthesis & Timing constraints Forward Error Correction (FEC), Bit Rate Error (BER) calculations Integrating Soft IP from Industry Standard and Custom IP into the design Bandwidth calculation Prefer experience with some of: LPDDR5 UFS/FlashPCIe Gen4/5

Easy Apply

Contract

90 - 130

LEAD ASIC DFT STAFF ENGINEER – REMOTE

Remote

•

Yesterday

Hiring: Lead ASIC DFT Staff Engineer Location: Remote PST Time Zone Experience: 10+ Years We are looking for a Lead/Staff ASIC DFT Engineer with strong hands-on experience in end-to-end Design-for-Test (DFT) for complex ASIC/SoC designs. Required Skills: SCAN / Scan Insertion / Scan Architecture / Scan Compression ATPG / ATPG Simulation / Fault Coverage / Diagnosis MBIST / LBIST / SMS TetraMAX / TMAX / DFTMAX Tessent DFT DRC / Debug Pattern Retargeting / Pattern Porting SDF / SDC / DFT

Easy Apply

Contract, Third Party

Depends on Experience

Lead ASIC DFT Staff Engineer

Remote

•

Yesterday

Position: Lead ASIC DFT Staff Engineer Location Remote (must be aligned with PST time zone) Long Term Experience:10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary: We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon valida

Easy Apply

Third Party, Contract

Depends on Experience

Lead ASIC DFT Staff Engineer at Remote

Remote

•

Yesterday

Job Title: Lead ASIC DFT Staff Engineer Location: Remote (must be aligned with PST time zone) Long Term Contract Job Description: We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug eff

Easy Apply

Contract, Third Party

90 - 100

Formal Verification

Ben Lomond, California

•

2d ago

JOB DUTIES: Participate in the functional verification of a block(s) of complex ASICs and/or IP cores for a combined CPU/GPU development effort. Be part of a team of design and verification engineers, working closely with other team members to understand and verify the functionality of a given design element within the context of the block, chip and overall system. Be responsible for carefully documenting and executing test plan(s) consisting of directed and constrained-random tests to be run du

Easy Apply

Contract, Third Party

Depends on Experience

High-Speed EDA/CAD Engineer (Analog & Mixed Signal)

Sunnyvale, California

•

16d ago

Position:High-Speed EDA/CAD Engineer (Analog & Mixed Signal) Location:Sunnyvale, CA Hybrid 3 days onsite (relocation candidates is fine) Duration:24+ month contract Domain:Analog & Mixed Signal EDA/CAD Job Description: Client is seeking an EDA/CAD Engineer to support and develop SiGe and CMOS design solutions for the high-speed analog ASIC design team. The engineer will be hands-on with all phases of tool flow, including PDK installation and support, tool support and installation, layou

Easy Apply

Contract

$60 - $70

ASIC jobs in California, USA