ASIC jobs in California

ASIC Subsystem Engineer (Mid-level or Lead)

El Segundo, California

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Today

ASIC Subsystem Engineer (Mid-level or Lead) Company: The Boeing Company The Boeing Space & Missions Systems Division is seeking a Mid-level or Lead ASIC Subsystem Engineer to join the Space and Launch Engineering team in El Segundo, California. In this role, you will support the design and development of advanced ASICs and mixed-signal components for space-based digital communication systems supporting commercial, civil, and national security programs. You will work with a highly motivated, m

Full-time

USD 119,850.00 - 162,150.00 per year

FPGA/ASIC Design Engineer (Silicon Engineering)

Irvine, California

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Today

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. FPGA/ASIC DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the worl

Full-time

USD 125,000.00 - 160,000.00 per year

Engineering Intern - ASIC DFT (Spring 2027 Co-Op)

Palo Alto, California

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Today

About Rivian Rivian is on a mission to keep the world adventurous forever. This goes for the emissions-free Electric Adventure Vehicles we build, and the curious, courageous souls we seek to attract. As a company, we constantly challenge what's possible, never simply accepting what has always been done. We reframe old problems, seek new solutions and operate comfortably in areas that are unknown. Our backgrounds are diverse, but our team shares a love of the outdoors and a desire to protect it

Full-time

USD 45.00 - 51.00 per hour

Engineering Intern - AI/ML ASIC CAD (Spring 2027 Co-Op)

Palo Alto, California

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Today

Full-time

USD 45.00 - 51.00 per hour

Physical Design Engineer Semiconductor / ASIC

Hybrid in Palo Alto, California

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10d ago

Physical Design Engineer Semiconductor / ASIC Location: Palo Alto, CA (100% Onsite) Openings: 5 Job Overview We are looking for an experienced Physical Design Engineer with strong hands-on expertise in end-to-end ASIC physical design and advanced semiconductor process nodes. The ideal candidate must have exposure to TSMC 2NP/3NP technology and proven experience in physical implementation, timing closure, power optimization, and physical verification. Key Responsibilities Execute the complete phy

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Contract

$70 - $90

ASIC DFT Engineer

Palo Alto, California

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Today

Full-time

Compensation information provided in the description

Lead ASIC DFT Staff Engineer

Remote

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Today

Job Description: Key Skills : "SCAN, ATPG, MBIST, Timing Simulations, SDF, SDC , PSV, Diagnosys , Pattern Retargeting , Pattern porting, DRCs, TetraMax, DFTMax " Experience: 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary: We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertio

Contract

USD70.0/HOURLY - USD80.0/HOURLY

ASIC/FPGA Design Verification Engineer

El Segundo, California

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Today

This posting is for a contract assignment and is not a full-time employment offer with Boeing. Candidates selected for roles will be employed as contract workers through a Boeing approved 3rd party for the duration of the specified project. Analyzes customer and system requirements to develop basic architectural approaches and detailed specifications for various electronic products. Develops high-level and detailed designs consistent with requirements and specifications. Validates designs throug

Full-time

ASIC/FPGA Verification Engineer 5

El Segundo, California

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Today

This posting is for a contract assignment and is not a full-time employment offer with Boeing. Candidates selected for roles will be employed as contract workers through a Boeing approved 3rd party for the duration of the specified project. Regular and predictable attendance is required Work statement is a non-managerial role, non-leadership role. Resolves complex issues on critical programs related to architectural approaches, requirements, specifications and design. Leads technical aspect of p

Full-time

ASIC/SOC DFT Engineer (Silicon Engineering)

Palo Alto, California

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Today

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. ASIC/SOC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world's

Full-time

USD 135,000.00 - 175,000.00 per year

ASIC RTL DESIGN Engineer

Remote

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4d ago

REMOTE OFFSITE: FROM HOME 2 Contract positions interviewing now, for Mid November start dates: 12-18 Months + CONTRACT SENIOR ASIC RTL Design (need ASIC-RTL Design not FPGA) Strong Verilog High Speed Memory Interface Experience AXI bus Multiclock Domain Designs Logic synthesis & Timing constraints Forward Error Correction (FEC), Bit Rate Error (BER) calculations Integrating Soft IP from Industry Standard and Custom IP into the design Bandwidth calculation Plusses: LPDDR5 UFS/Flas.1 PCIe Gen3/4/

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Contract

100 - 140

ASIC Design Lead / Senior Chip Design Engineer

Remote

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11d ago

Role:ASIC Design Lead / Senior Chip Design Engineer Location:REMOTE Duration: 12 months Contract Job Description What Youll Do Architecture and Chip Definition Lead ASIC architecture development from high-level requirements and block diagrams. Work with system architects to define chip functionality, interfaces and performance goals. Write detailed specifications for chip components and subsystems. RTL Design and Synthesis Develop RTL designs and run synthesis with Synopsys Design Compiler. Tun

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Contract

95 - 105

ASIC/RTL Design Engineer 5

San Jose, California

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5d ago

ASIC/RTL Design Engineer 5 - 2 - San Jose Experience - 10+ Years preferable JOB DUTIES: You will build behavioral models of analog and mixed-signal circuits (PLLs, clocking, ADC/DAC, TX/RX analog front ends, calibration loops) in SystemVerilog. Those models drop into a SystemVerilog UVM verification environment used for high-speed SerDes and SoC IP. You will work closely with analog circuit designers, RTL designers and verification engineers. Successful candidates will be responsible for leadin

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Third Party, Contract

Depends on Experience

ASIC Design Verification Engineer - W2 Contract

Menlo Park, California

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4d ago

Job Details ASIC Design Verification Engineer 12+ Months Contract with Possible Extension Austin, TX & Menlo park, CA Job Summary We are seeking a highly motivated ASIC Design Verification Engineer to join our silicon engineering team. The ideal candidate will have strong experience in SystemVerilog/UVM-based verification of complex IPs or SoCs and will be responsible for developing test cases, debugging RTL issues, and driving coverage closure. Responsibilities Maintain reusable SystemVerilog/U

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Contract

Depends on Experience

Lead ASIC DFT Staff Engineer

Remote

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18d ago

Required Skills & Qualifications: Strong hands-on experience in ASIC DFT with end-to-end ownership.Solid understanding of DFT fundamentals, fault models, test techniques, and test coverage concepts.Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug.Hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools.Proven experience in scan insertion, ATPG setup, simulation, debug, and DRC analysis.Experience with MBIST implementation and verific

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Third Party, Contract

90 - 100

Physical Design Engineer

Sunnyvale, California

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3d ago

Job Title: Physical Design Engineer Location: San Jose, CA Job Description: Need a PDE with front end experience who is good with Synthesis, PDE flow and placement optimization. We are hiring an experienced Physical Design Engineer to join a high-performing silicon engineering team supporting one of the world's leading technology organizations in Sunnyvale, CA. This is an exciting opportunity to work on cutting-edge ASIC/SoC designs and collaborate with talented engineers throughout the chip de

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Full-time, Part-time, Contract, Third Party

ASIC Verification Engineer (UVM & GLS Focus)

Remote

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12d ago

Must-Have SkillsStrong end-to-end UVM expertise with hands-on experience building verification environments from scratch, including testbench architecture, agents, sequences, monitors, scoreboards, checkers, assertions, coverage models, and regression automation.Extensive Gate-Level Simulation (GLS) experience including SDF annotation, timing validation, X-propagation analysis, reset/clock synchronization issues, power-up sequence validation, and debug of post-synthesis/post-layout simulation fa

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Contract

65 - 70

Physical Design Engineer

Sunnyvale, California

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3d ago

Job Title: Physical Design Engineer Location- Sunnyvale, CA- Onsite Need a PDE with front end experience who is good with Synthesis, PDE flow and placement optimization. Key Responsibilities Drive RTL synthesis and optimization to achieve performance, power, and area (PPA) goals Perform floor planning for complex ASIC/SoC designs while ensuring optimal timing, congestion, and power distribution Collaborate closely with RTL design engineers to provide actionable feedback that improves RTL qualit

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Contract, Third Party

ASIC Verification Engineer (UVM & GLS Focus)

Remote

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19d ago

Job Description: Must-Have Skills Strong end-to-end UVM expertise with hands-on experience building verification environments from scratch, including testbench architecture, agents, sequences, monitors, scoreboards, checkers, assertions, coverage models, and regression automation.Extensive Gate-Level Simulation (GLS) experience including SDF annotation, timing validation, X-propagation analysis, reset/clock synchronization issues, power-up sequence validation, and debug of post-synthesis/post-la

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Contract

Depends on Experience

Recruiter - Senior Technical Sourcer

Rancho Cordova, California

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Today

Job Title: Recruiter Duration: 6 Months Contract Location: Portland, OR / Phoenix, AZ / Longmont, CO / Rancho Cordova, CA Position Summary As Senior Technical Sourcer, you will build proactive talent pipelines and market intelligence for highly specialized semiconductor and technology roles that are critical to Client's hiring strategy. This role focuses on identifying, engaging, and qualifying passive talent across hard-to-fill engineering disciplines, including NAND, SSD, firmware, ASIC,

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Contract, Third Party

ASIC jobs in California, USA