ASIC jobs in San Jose, CA

Sunnyvale, California

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Today

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. SR. ASIC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world's

Full-time

USD 175,000.00 - 280,000.00 per year

Senior ASIC Design Engineer - Clocks IP

Santa Clara, California

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Today

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI - the next era of computing. NVIDIA is a learning machine" that constantly evolves by adapting to new opportunities that are hard to solve, that only we can take on, and that matter to the world. This is our life's work, to amplify human

Full-time

USD 136,000.00 - 218,500.00 per year

Top Priority Role --- Remote --- Lead ASIC DFT Engineer

San Jose, California

•

Today

Good Afternoon, My name is Shivam and I am reaching out from Tanisha Systems Inc. If you are looking for new roles, then please look at below job description. If feel comfortable, then please share updated copy of resume. Title - Lead ASIC DFT Engineer Location Remote (must be aligned with PST time zone) Experience: 15+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug ad

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Contract, Third Party

Depends on Experience

ASIC IP Application Engineer

San Jose, California

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10d ago

Maxonic maintains a close and long-term relationship with our direct client. In support of their needs, we are looking for a Senior Application Engineer. Job Description: Job Title: Senior Application Engineer Job Type: Contract Job Location: San Jose, CA Work Schedule: On-site Pay Rate: $65 W2 & $75 C2C, Based on experience Description: The CAD team is looking forhighly analytical and detail-oriented Application Engineer, having an understanding on ASIC Design and building blocks used in suc

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Contract

Depends on Experience

ASIC Verification (Onsite In Bay area )

Santa Clara, California

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25d ago

Quick feedback One to two interview process Microsoft Teams MUSTbe able to work onsite inSanta Clara no exceptions Key points: UVM Systemverilog 10+ years of exp Onsite in Santa Clara 1 year We are looking forstrong SoC DVcandidates to work onsite in San Jose. System-level experience is highly preferred. Familiarity withAXI4 is preferred Strong SystemVerilog and UVM skillsScripting experience (Python/Perl/Shell) is a plusC-based programming experience is a strongplusExperience with infrastru

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Contract, Third Party

70 - 90

Senior ASIC Design Architect

San Jose, California

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Today

Candidates must be currently authorized to work in the United States on a full-time, permanent basis. StaffRight Associates and our clients do not provide visa sponsorship for this position. PLEASE DO NOT APPLY IF YOU DO NOT MEET THESE ABOVE QUALIFICATIONS Base pay, bonus, outstanding retirement programs! The MissionStaffRight Associates has been retained to lead an exclusive search for a Senior ASIC Design Architect to spearhead the development of custom, high-performance silicon for next-gene

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Full-time

180000 - 230000

ASIC Physical Design Engineer

San Jose, California

•

Today

Candidates must be currently authorized to work in the United States on a full-time, permanent basis. StaffRight Associates and our clients do not provide visa sponsorship for this position. PLEASE DO NOT APPLY IF YOU DO NOT MEET THESE ABOVE QUALIFICATIONS Great base pay, bonus, terrific benefits and exceptional 401k! he MissionStaffRight Associates is recruiting to identify a high-caliber ASICPhysical Design Engineer to spearhead the structural realization of next-generation System-on-Chip (So

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Full-time

170000 - 220000

ASIC / SoC RTL Design Engineer

San Jose, California

•

Today

SoC RTL Design Engineer San Jose, CA: 100% Onsite 6 + Months $60-$62.50/HR Role: Lead advanced CMOS SoC design using ARM, PCIe, DDR, and Ethernet. Responsibilities: Architecture definition and micro-specs RTL coding, verification, and debug Synthesis, timing closure, and bring-up Requirements: ASIC design flow experience Expert RTL coding/debugging Dexian stands at the forefront of Talent + Technology solutions with a presence spanning more than 70 locations worldwide and a team exceeding 10,

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Contract

$60 - $62.50 per hour

Lead ASIC DFT Engineer

Remote

•

Today

Job Title: Lead ASIC DFT EngineerLocation: Remote (PST time zone)Duration: 12 Months Key skills for Lead ASIC DFT: SCAN, ATPG, MBIST, Timing Simulations, SDF, SDC , PSV, Diagnosys , Pattern Retargeting , Pattern porting, DRCs, TetraMax, DFTMax Experience:10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary:We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This

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Contract, Third Party

Depends on Experience

ASIC RTL Design Engineer - Onsite

San Jose, California

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21d ago

Title: ASIC RTL Design Engineer - Onsite Mandatory skills: SoC Architecture, ASIC design flow, RTL coding, debugging, verification, supporting synthesis, timing closure, ARM cores, I/O standard interfaces, Ethernet, DDR, DMA, PCIE, SATA, internal IPs, digital CMOS processes, SoC design, Chip definition, Architecture development, modeling, micro-architectural specifications, micro-architectural specifications, logic implementation, emulation, debug Description: JOB DUTIES: The work will expose th

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Contract

57 - 62

Principal Analog Mixed Signal ASIC Layout Engineer

Remote or Cambridge, Massachusetts

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Today

Principal Analog Mixed Signal ASIC Layout Engineer 12+month contract No security clearance required. Cambridge, MA - Hybrid work is acceptable; however, candidates must be able to work onsite at least once a week. Overview Seeking a talented and motivated individual to join the Analog Mixed Signal (AMS) ASIC team at client. The physical silicon design group is responsible for creating complex analog layouts from schematics, collaborating with other members of our exceptional team. These lay

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Contract

Senior FPGA/Emulation Validation Engineer - Fulltime

Hybrid in San Jose, California

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19d ago

Job Title : Senior FPGA/Emulation Validation EngineerLocation : San Jose, CA, USA (Hybrid)Job Type : Full-timeDepartment: Verification Job DescriptionThe Senior FPGA/Emulation Validation Engineer position is your opportunity to join one of the industry s leading companies in platform security management and ransomware detection for cloud datacenters, 5G infrastructure and disaggregated compute ecosystems. You should have prior knowledge about SOC architecture, and emulation and prototyping platf

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Full-time

Depends on Experience

ASIC/RTL Design Engineer

Hybrid in San Jose, California

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20d ago

ASIC/RTL Design Engineer Location: San Jose, CA Duration : 12 months plus JOB DUTIES: The work will expose the designer to a number of IP including ARM cores, Ethernet, DDR, DMA, PCIE, SATA Successful candidates will be responsible for leading, and participating in, the design of leading edge SoCs in advanced digital CMOS processes. Our RTL Design Engineers are expected contribute in all aspects of SoC design including: Chip definition, Architecture development and modeling, Development of micr

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Contract

Depends on Experience

Lead ASIC DFT Engineer

Remote

•

Today

Title - Lead ASIC DFT Engineer Location Remote (must be aligned with PST time zone) Duration - Contract Job Description Experience 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary We are seeking a highly experienced Lead ASIC DFT Engineerto architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundar

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Third Party, Contract

$75 - $80

ASIC DFT Engineer

Remote

•

7d ago

Title - Lead ASIC DFT Engineer Location Remote (must be aligned with PST time zone) Belowis the detailed jobdescription for your reference -Job Description: Experience10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary We are seeking a highly experienced Lead ASIC DFT Engineerto architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LB

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Contract, Third Party

Depends on Experience

Lead ASIC DFT Engineer

Remote

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4d ago

Role: Lead ASIC DFT Engineer Location Remote preferred PST otherwise anywhere in USA Duration: 12+ month contract Job Description Key skills for Lead ASIC DFT: SCAN, ATPG, MBIST, Timing Simulations, SDF, SDC , PSV, Diagnosys , Pattern Retargeting , Pattern porting, DRCs, TetraMax, DFTMax Experience 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary We are seeking a highly experienced Lead ASIC DFT Engineerto architect, implement, verify, and debug advanced DFT solutio

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Contract

Depends on Experience

Lead ASIC DFT Engineer

Remote

•

19d ago

Title - Lead ASIC DFT Engineer Location Remote (must be aligned with PST time zone) Job Description Experience 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary We are seeking a highly experienced Lead ASIC DFT Engineerto architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation,

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Third Party, Contract

Depends on Experience

Physical design Engineer

San Jose, California

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4d ago

Job Title:Senior Principal Physical Design Engineer (Top-Level Floorplanning & STA) Location: San Jose / Austin Job Type: Onsite Experience : Relevant minimum 7+ years required and senior also fine. Responsibilities Own the full-chip top-level floorplan: die/partition planning, macro and memory placement, and pin/port alignment across block boundaries Define partition abutment, repeating structures, and channel/feedthrough strategy to enable clean block integration Drive top-level PPA optim

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Contract

Depends on Experience

Product Planning Engineer-ASIC/SoC

San Jose, California

•

Today

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the wo

Full-time

USD 140,000.00 per year

Senior Custom ASIC Engineering Lead

San Jose, California

•

Today

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Are you a versatile, senior engineer capable of leading external and internal cross-functional teams in areas such as physical design, STA, DFT, and packaging? Have you taped out so many chips that you can identify potential design problems hidden in E

Full-time

USD 143,800.00 - 230,000.00 per year

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ASIC jobs in San Jose, CA, USA