ASIC Jobs in San Jose, CA

1 - 20 of 27 Jobs

ASIC/FPGA Design ConsultantJob Title - ASIC/FPGA Design Consultant

SA Technologies IncCompany Name - SA Technologies Inc

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Remote or Sunnyvale, CA, USA

Contract

Job title: ASIC/FPGA Design Consultant Est. Duration: 12+ months to Extension Direct Client Semi-Conductor Domain USA Remote role Job Function Collaborate with architecture, and integration teams to create new highly integrated multi-core heterogeneous compute platform (ACAP)Someone in US with USB 4 emulation/ prototyping expertiseMicro architecture and RTL designWrite optimal timing constraints (SDC)Run design sanity checker toolsWork closely with physical design team during implementationDoc

ASIC Design EngineerJob Title - ASIC Design Engineer

JobotCompany Name - Jobot

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Santa Clara, CA, USA

Full-time

ASIC Design Engineer Needed / Santa Clara CA/ - Interviewing Now! This Jobot Job is hosted by: Kevin Szilagyi Are you a fit? Easy Apply now by clicking the "Apply Now" button and sending us your resume. Salary: $150,000 - $220,000 per year A bit about us: We are a leading developer of visual AI products. Our technologies enable a wide variety of human and computer vision applications, including video security, advanced driver assistance systems (ADAS), electronic mirror, drive recorder, driv

ASIC RTL / SoC Design EngineerJob Title - ASIC RTL / SoC Design Engineer

TetraMem IncCompany Name - TetraMem Inc

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Fremont, CA, USA

Full-time

Responsibilities: Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring robust and efficient designs. Integrate and validate IP blocks within the larger system, ensuring seamless functionality and compatibility. Thoroughly comprehend both internal and external requirements, conducting Power, Performance, and Area (PPA) analysis to optimize design trade-offs. Collaborate closely with the backend team, participating in RTL coding, implementation, and synthe

ASIC/SoC Design Verification EngineerJob Title - ASIC/SoC Design Verification Engineer

TetraMem IncCompany Name - TetraMem Inc

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Fremont, CA, USA

Full-time

Responsibilities: Collaborate with design engineers and architects to define, document and implement detailed test plans for the SoC design verification. Build and maintain infrastructure/environment for automation verification of SoC architecture, function and performance. Develop reusable testbench, constrained-random/directed testcases, and verification associated behavioral module for both of block levels and system levels. Develop regression strategy, methodology and tools(scripts). Define

Sr. Field Application Engineer (ASIC Design) in San Jose CAJob Title - Sr. Field Application Engineer (ASIC Design) in San Jose CA

EpiksoCompany Name - Epikso

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San Jose, CA, USA

Full-time

Field Application Engineer (ASIC Design) San Jose CA . It's onsite role Direct Hire permanent role Base Salary Range is $2,25,000-$2,50,000 The salary midpoint for this position is $2,37,500. This compensation range is specific to the locality of the job. The midpoint is just for your reference because the salary of a person hired into the role may be above or below that rate. The actual salary paid to an individual will be based on multiple factors, including, but not limited to, specific skill

ASIC STA / Timing EngineerJob Title - ASIC STA / Timing Engineer

Xoriant CorporationCompany Name - Xoriant Corporation

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San Jose, CA, USA

Contract

Job Title: ASIC STA / Timing Engineer Location: San Jose, CA (3 days onsite) Duration: 6+ months (Long Term Project + Possible Extension) Rate:$100/hr on w2 without benefits Description What You’ll Do You will be responsible for all aspects of timing including, working with designers for timing constraints generation, helping construct/modify flows, timing analysis and timing closure. 15+ years’ experience in chip design Deep technical knowledge of Static timing Analysis (STA)10+ years’ exper

ASIC Emulation Engineer (HAPS)Job Title - ASIC Emulation Engineer (HAPS)

Technical LinkCompany Name - Technical Link

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Remote

Contract

Skills and Responsibilities: ASIC/IP RTL to Emulation platforms Zebu/Haps (preferred), Palladium/ProtiumBuild emulation model from released RTLGenerate target platform loadable image(s) test and release the image to Firmware and DV teams.Run sanity tests for qualifying release of the image(s)Release the model to various team including Functional Validation team, Firmware, DVAssist debug of failures providing instrumented model (Waveform Dumps, in circuit debug) and interfacing with key stakehol

ASIC/FPGA Verification EngineerJob Title - ASIC/FPGA Verification Engineer

Xoriant CorporationCompany Name - Xoriant Corporation

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San Jose, CA, USA

Contract

Job Title: ASIC/FPGA Verification Engineer Location: San Jose, CA Duration: 6+ months (Possible Extension-Long Term Project) Rate: $115/hr on w2 Description Participate in internal design and code reviewsSetup complete verification environmentDevelop test plans and creating testsPerform code and functional coverage and analyze coverage reportsSetup and run gate level simulations with SDFRequirements Master's degree7 years of ASIC/FPGA verification experience using one of the common verification

ASIC Design Engineer (Linting)Job Title - ASIC Design Engineer (Linting)

Technical LinkCompany Name - Technical Link

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Remote

Contract

As a member of our engineering community, your primary responsibility will be to verify ASIC implementations for timing and ASIC Design Audits (Lint, CDC, DFT, etc.) at the block and full chip level. Duties & Responsibilities: General ASIC development Participate in the RTL implementation, synthesis, formality check as well as ECOsSupport post-layout timing closure and verificationDetailed ASIC Back-End Development Support the design team to develop Block / Full Chip Level Constraints, verify t

ASIC Verification EngineerJob Title - ASIC Verification Engineer

Q1 Technologies, Inc.Company Name - Q1 Technologies, Inc.

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Remote or Santa Clarita, CA, USA

Full-time, Third Party, Contract

Job Title : ASIC Verification Engineer Location: Bay Area, CA & Austin, Texas (Onsite only) Opening 10 Mandatory Skills: Design Verification, UVM, IP, SOC, System Verilog Job Description: Experience in pre-silicon RTL Verification /IP Verification / SOC verification Strong knowledge of System Verilog and working knowledge of recent verification methodologies (UVM) Domain expertise in one or more of the following areas System-on-a-chip verification with multiple CPUs and fixed function units

ASIC Verification Engineer - UVM from scratchJob Title - ASIC Verification Engineer - UVM from scratch

Softworld, Inc.Company Name - Softworld, Inc.

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Remote

Contract

Title: ASIC Verification Engineer - UVM Location: Cambridge MA (remote is available) Duration: 12 months with likely extensions Clearance: Active preferred, will process for secret clearance if needed Main requirement: Ability to create a UVM testbench from scratch. Overview: Draper's Digital Design Team is seeking a motivated and experienced Senior Verification Engineer to tackle novel verification challenges in FPGAs and ASICs. In this role, you will apply modern verification strategies to

PCB TechnicianJob Title - PCB Technician

HCL America Inc.Company Name - HCL America Inc.

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San Jose, CA, USA

Full-time

Responsible for testing ASIC, uploading test logs, inventory tracking, supporting, PCB troubleshooting down to component level, conducting diagnostics, or maintaining hardware. Additional duties will be working to ensure that the testing stations are up and running correctly and making modifications as needed and respond to internal customer needs.

Senior DFT Application EngineerJob Title - Senior DFT Application Engineer

Judge Group, Inc.Company Name - Judge Group, Inc.

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Fremont, CA, USA

Full-time

Location: Fremont, CA Salary: $100,000.00 USD Annually - $250,000.00 USD Annually Description: Our client is seeking a Senior DFT Application Engineer for a permanent/direct position in the CA Bay area. Qualified candidates may email RESPONSIBILITIES/TASKS: Drive products into customer projects through to adoption by creating methodology and flows; this may include infrastructure and integration into a customer's environment and the identification of pilot projects for tool use and the debug

Formal Verification EngineerJob Title - Formal Verification Engineer

Technical LinkCompany Name - Technical Link

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Remote

Contract

I'm looking for an ASIC engineer to do Formal Verification. Somebody with an architectural background. Manager said “A senior/expert” Tools: Jasper/Jasper Gold, VC Formal, The candidate will create their own test bench. They’re taking the product from Specs to finish. Verilog, Systems Verilog, UVM

Functional Safety Manager (FuSa)Job Title - Functional Safety Manager (FuSa)

Xoriant CorporationCompany Name - Xoriant Corporation

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Remote

Contract

Funcitonal Safety Manager (FuSa) Duration: Long term Location: Sunnyvale CA Description : Looking for Functional Safety Manager (FuSa), encompassing FPGA and ASIC designs. Electronics domain ISO26262 functional safety standard Siva Kumar. CH P: +1 E:

Sr. RTL Design EngineerJob Title - Sr. RTL Design Engineer

Triton R&D Consulting, LLCCompany Name - Triton R&D Consulting, LLC

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San Jose, CA, USA

Full-time

The responsibilities will include: Responsibility is the design, simulations and integration video centric IPs and related chip activities.Opportunities include cutting-edge IP in the area of SerDes, Display Port, HDMI, USB4 and Type C IP’s.Must work closely with the architecture team to find architectural tradeoffs of area, performance, power and the most state-of-the-art solutions.Will be responsible the micro-architecture, RTL implementations, simulations and trial synthesesWill be responsib

Design Verification Engineer - San Jose, CA | Austin, TXJob Title - Design Verification Engineer - San Jose, CA | Austin, TX

Canvendor IncCompany Name - Canvendor Inc

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San Jose, CA, USA

Contract, Third Party

Role: Design Verification Engineer Job Location: San Jose, CA | Austin, TX Duration: 12+ Months JOB DESCRIPTION As a Contract Design Verification Engineer, you will contribute to the functional verification of GPU IP. This is a hands-on role, driving next generation product development with a high level of contribution and knowledge base needs. Key responsibilities may include: • GPU top level verification test plan development and execution: • Work with RTL and unit level DV teams to de

Electrical Engineer (Senior/Staff/Principle)Job Title - Electrical Engineer (Senior/Staff/Principle)

Kforce Technology StaffingCompany Name - Kforce Technology Staffing

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San Jose, CA, USA

Third Party, Contract

RESPONSIBILITIES: Kforce has a client in San Jose, CA that is seeking an Electrical Engineer at the Senior, Staff, or Principle level. This is an opportunity to join the team for an exciting career on the cutting edge in data storage and server product design. Summary: In the beginning of any project, the workload is a lot of design, diagrams, compare and analyze. From the PCB to the peripheral systems that interact with the PCB. This person will work with the layouts and engineering team to de

Firmware EngineerJob Title - Firmware Engineer

EndoSec LLCCompany Name - EndoSec LLC

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Remote

Full-time

Firmware Engineer The Firmware Engineer will be responsible for designing, developing, testing, and maintaining embedded software that operates on microcontrollers and other hardware platforms. The primary focus will be on creating efficient, reliable, and scalable firmware solutions to enable the functionality of various electronic devices and systems. The candidate is expected to work with teams of diverse backgrounds including mathematicians, cryptographers, and hardware engineers, as well as

ASIC RTL DesignerJob Title - ASIC RTL Designer

Technical LinkCompany Name - Technical Link

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Remote

Contract

Job Description: Who We Want: The ideal candidate will be creative and highly motivated. They will know the difference between getting a job done and getting a job done properly. Knowing the tools and how to code is not enough. The right candidate will understand that quality matters in everything that they produce. The candidate will be a creator and not an integrator. They must understand how to deliver professional quality code on a predictable schedule. Job Responsibilities: Contribute to th