ATPG jobs in Palo Alto, CA

San Jose, California

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Today

We are looking for Senior SoC Validation Engineer for our client in San Jose, CAJob Title: Senior SoC Validation Engineer Job Location: San Jose, CA Job Type: Contract Pay Range: $72.35hr - $76.36hr Job Overview: We are seeking a senior-level contractor to lead production test development for SoC devices integrating copackaged optics (CPO) SerDes interfaces. This role centers on ATE program development, DFT/BIST enablement, yield/quality optimization, and high-volume manufacturability. Strong un

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Third Party, Contract

Depends on Experience

Senior DFT Engineer

Santa Clara, California

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Today

Job Description: 5+ years of hands-on experience in DFT and ATPG for SoC or ASIC designs Strong understanding of DFT fundamentals including controllability, observability, and scan-based testing Proven expertise in ATPG pattern generation, analysis, and debug Experience with MBIST, including memory test architectures and diagnostics Knowledge of IO Test methodologies for interface and pin level validation Solid understanding of clock DFT and clock verification concepts Strong grasp of digital de

Full-time

USD130000.0/ANNUAL - USD150000.0/ANNUAL

Design For Test (DFT) Engineer

San Jose, California

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Today

Job Description Onsite San Jose - 5 days a week Description The team is looking for a Design-for-Test contractor to test and validate the next generation Samsung chips. Candidate will be responsible to work with Front End and Physical Design teams to implement DFT and test designs which will impact the product lines for radio frequency (RF) and BlueTooth/Wireless LAN chipsets. JOB RESPONSIBILITIES: Experience with memory BIST - Siemens Tessent Flow Experience with gate-level simulation and si

Contract

DFT Engineer in San Jose, CA (Hybrid role)

Hybrid in San Jose, California

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Yesterday

Role: DFT Engineer Location: San Jose, CA (Hybrid role) Duration: 12+ months Job description: Good understanding of DFT fundamentals and methodologyExperience with DFT insertion and verificationExperience with Tessent tools:Tessent Streaming Scan Network Op SWTessent Memory BIST-NS Ap SWTessent Memory BIST-NS repair Op SWTessent Test Kompress Ap SWTessent IJTAG Ap SWTessent Scan Pro Ap SWAbility to work under pressure and debug issues promptly

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Contract, Third Party

Depends on Experience

Validation Engineer 3 # 26-26845

San Jose, California

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Today

Duration: 12-month contract Job Description:We are seeking a senior-level contractor to lead production test development for SoC devices integrating copackaged optics (CPO) SerDes interfaces.This role centers on ATE program development, DFT/BIST enablement, yield/quality optimization, and high-volume manufacturability.Strong understanding of SerDes and protocols such as UCIe and PCIe is required, with emphasis on translating characterization into robust, multisite production tests.Experience wi

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Contract

$75 - $85

Design For Test (DFT) Engineer

San Jose, California

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Yesterday

Role: Design For Test (DFT) Engineer Location: San Jose, CA (Onsite: M-F) Duration: 6 Months Contract Pay Rate: $100-130/hr W2 Description: Looking for a Design-for-Test contractor to test and validate the next generation chips. Candidate will be responsible to work with Front End and Physical Design teams to implement DFT and test designs which will impact the product lines for radio frequency (RF) and BlueTooth/Wireless LAN chipsets. Job Responsibilities: Experience with memory BIST Siemens

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Contract

100 - 130

Test Engineer-Various Levels

San Jose, California

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Today

Overview Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to hire exceptional Test Engineers to join our Operations team in San Jose. In this role, you will be working with some of the brightest inventors and engineers in the world developing products that make data faster and safer. Rambus offers a flexible work environment, embracing a hybrid approach for most office-based roles. Employees are encouraged to spend an average of at least three days per wee

Full-time

USD 126,000.00 - 234,000.00 per year

CPU Gate Level Synthesis Engineer

Santa Clara, California

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Today

Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hard-working people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products! The same passion for innovation that goes into our products also applies to our p

Full-time

CPU Core Staff DFT Engineer

Santa Clara, California

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Today

ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world's most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you're designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger - technology that moves the world forward. Joi

Full-time

USD 175,000.00 per year

DFT Engineer

San Jose, California

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Today

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Broadcom's Core Switching Group division is seeking a candidate for a DFT engineer. Products include networking switches for Scale up and Scale Out for traditional and AI data centers. This position is at our R&D center in San Jose, CA. The successful

Full-time

USD 121,900.00 - 195,000.00 per year

DFT Engineers - Santa Clara, CA

Santa Clara, California

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30+d ago

Job Title: DFT Engineers Location: Santa Clara, CA Job Description: 5+ years of hands-on experience in DFT and ATPG for SoC or ASIC designsStrong understanding of DFT fundamentals including controllability, observability, and scan-based testingProven expertise in ATPG pattern generation, analysis, and debugExperience with MBIST, including memory test architectures and diagnosticsKnowledge of IO Test methodologies for interface and pin level validationSolid understanding of clock DFT and clock ve

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Contract

Depends on Experience

Senior ATE Production Test Engineer – SerDes / Co-Packaged Optics (CPO)

Hybrid in San Jose, California

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Today

Senior ATE Production Test Engineer SerDes / Co-Packaged Optics (CPO)Location: San Jose, CA Fully Onsite Experience: 6+ years preferred Role OverviewWe are seeking a hands-on Production Test Engineer to develop and optimize automated test equipment (ATE) programs for SoC devices featuring SerDes interfaces and Co-Packaged Optics (CPO). The engineer will lead production test development for wafer sort and final test, focusing on design-for-test (DFT), built-in self-test (BIST), yield optimizati

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Contract

55 - 60

Engineering Intern - ASIC DFT (Spring 2027 Co-Op)

Palo Alto, California

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Today

About Rivian Rivian is on a mission to keep the world adventurous forever. This goes for the emissions-free Electric Adventure Vehicles we build, and the curious, courageous souls we seek to attract. As a company, we constantly challenge what's possible, never simply accepting what has always been done. We reframe old problems, seek new solutions and operate comfortably in areas that are unknown. Our backgrounds are diverse, but our team shares a love of the outdoors and a desire to protect it

Full-time

USD 45.00 - 51.00 per hour

Senior Product, Test and Yield Enhancement Engineer - Taiwan

Sunnyvale, California

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Today

Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. This architecture allows Cerebras to deliver industry-leading training and inference speeds; over 10 times faster than GPU-based hyperscale cloud inference services. This order of magnitude increase in speed is transforming the user experience of AI applications, unlocking real-time iteration and increasing intelligence via additional agentic computation. Cerebras works with the leading model labs, global enterprise

Full-time

Senior ATE Security Engineer, Amazon Leo Silicon Team

Sunnyvale, California

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Today

Amazon Leo is an initiative to launch a constellation of Low Earth Orbit satellites that will provide low-latency, high-speed broadband connectivity to unserved and underserved communities around the world.Come work at Amazon!The RoleAs a Senior ATE Security Engineer, you will engage with an experienced cross-disciplinary staff to deliver secure, high-quality custom silicon powering the Leo network. This role has two focuses: device security and provisioning during test, and the development of r

Full-time

CPU DFT Engineer

Santa Clara, California

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Today

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > CPU Engineering General Summary: As a DFT Engineer you will work with chip architects, chip designers, implementation engineers and test engineers to verify the DFT and DFD (Design for Debug) architecture, implementation, and test plans for both mixed signal and digital VLSI designs. Then you'll insure it becomes reality. We're doing a ground up implementation of a new chip architecture, so you'll have to

Full-time

USD 142,200.00 - 213,400.00 per year

Sr. Staff Engineer, ASIC Design

San Jose, California

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Today

Sr. Staff Engineer, ASIC Design Location: San Jose (on-site) Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using light instead of electricity to move data faster, further, and with a fraction of the energy needed to fuel the explosive growth of AI models. Backed by industry giants like NVIDIA, AMD and Intel and manufactured in partnership with the world's leading semiconductor ecosystem, Ayar Labs' co-packaged o

Full-time

USD 180,000.00 - 223,000.00 per year

ASIC DFT Engineer

Palo Alto, California

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Today

Full-time

Compensation information provided in the description

DFT Lead Engineer

San Jose, California

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Today

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Principal DFT Engineer Broadcom's ASIC Product Division is seeking candidates for a DFT position at our San Jose, California, Development Center. The successful candidate will be responsible for leading DFT programs all the way from chip level DFT spe

Full-time

USD 143,800.00 - 230,000.00 per year

ASIC/SOC DFT Engineer (Silicon Engineering)

Palo Alto, California

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Today

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. ASIC/SOC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world's

Full-time

USD 135,000.00 - 175,000.00 per year

ATPG jobs in Palo Alto, CA, USA