81 results (10 new)
San Jose, California
•
3d ago
Familiarity with the Siemens suite of DFT toolsDFT insertion for SCAN (with SSN) and MBISTMBIST Repair Implementation and VerificationGenerating collaterals for Test Timing and Place and RouteExpertise in IJTAG 1687 standard and good at understanding ICL and PDL standard SpecVerification of DFT features includingBoundary ScanJTAGSCANMBISTHigh Speed IOATPGDRC debugCoverage AnalysisPattern Generation for different fault models
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Full-time
110000 - 160000
Santa Clara, California
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14d ago
Job Title : Senior DFT Engineer Location : Santa Clara, CA Experience : 4+ Years in DFT Skill: [ATPG , MBIST, IO Test, Clock Verification] Job Summary We are seeking an experienced Senior DFT / ATPG Engineer to support highperformance GPU and SoC designs. The role focuses on delivering robust Design for Testability (DFT) solutions, comprehensive ATPG, and advanced test features such as MBIST, IO Test, and Clock Verification, ensuring high coverage, yield, and silicon reliability. The enginee
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Contract, Third Party
$60 - $70
Santa Clara, California
•
3d ago
Hi, Job Title : Senior DFT Engineer [ATPG , MBIST, IO Test, Clock Verification] Location : Santa Clara, CA Experience : 4+ Years in DFT Job Summary We are seeking an experienced Senior DFT / ATPG Engineer to support client s highperformance GPU and SoC designs. The role focuses on delivering robust Design for Testability (DFT) solutions, comprehensive ATPG, and advanced test features such as MBIST, IO Test, and Clock Verification, ensuring high coverage, yield, and silicon reliability. The engin
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Third Party, Contract
Depends on Experience
Santa Clara, California
•
7d ago
JobTitle:SeniorDFTEngineer[ATPG,MBIST,IOTest,ClockVerification] Location:SantaClara,CA Experience:4+YearsinDFT JobSummary WeareseekinganexperiencedSeniorDFT/ATPGEngineertosupportNVIDIAshighperformanceGPUandSoCdesigns.TherolefocusesondeliveringrobustDesignforTestability(DFT)solutions,comprehensiveATPG,andadvancedtestfeaturessuchasMBIST,IOTest,andClockVerification,ensuringhighcoverage,yield,andsiliconreliability.TheengineerwillworkcloselywithNVIDIAscrossfunctionalteamstoenablefirsttimerightsilico
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Contract
Depends on Experience
Santa Clara, California
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13d ago
Key Responsibilities: Develop and execute verification plans for DFx features including: Scan (stuck-at, transition fault) MBIST / LBIST Boundary Scan (JTAG) Memory repair and redundancy Low-power test scenarios Create and maintain testbenches using SystemVerilog/UVM for DFx validation. Verify: Scan chain integrity and connectivity Test mode functionality and coverage ATPG pattern validation and debug BIST controllers and memory test logic Technical Skills & Expertise: Strong knowledge of DFT/DF
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Third Party, Contract
Depends on Experience
ITsutra, Inc.
Santa Clara, California
•
6d ago
Senior DFT Engineer [ATPG, MBIST, IO Test, Clock Verification]Client- ConfidentialLocation: Santa Clara, CAOnsiteExperience: 4+ Years in DFT Job SummaryWe are seeking an experienced Senior DFT / ATPG Engineer to support NVIDIA s highperformance GPU and SoC designs. The role focuses on delivering robust Design for Testability (DFT) solutions, comprehensive ATPG, and advanced test features such as MBIST, IO Test, and Clock Verification, ensuring high coverage, yield, and silicon reliability. The e
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Contract
$70 - $90
San Jose, California
•
Today
Job Detail :- Required Skills & Qualifications 5+ years of hands-on experience in DFT and ATPG for SoC or ASIC designs Strong understanding of DFT fundamentals including controllability, observability, and scan-based testing Proven expertise in ATPG pattern generation, analysis, and debug Experience with MBIST, including memory test architectures and diagnostics Knowledge of IO Test methodologies for interface and pin level validation Solid understanding of clock DFT and clock verification co
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Full-time
Depends on Experience
Santa Clara, California
•
Today
Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our pr
Full-time
Cupertino, California
•
Today
Are you interested in working on tools and software that directly enable hardware validation? Our Hardware Test Engineering team is evolving our Design for Test (DFT) methodology, and we're building the software infrastructure to support it effectively.\\n This is an opportunity to develop software tools that control and automate hardware testing. You'll work on designing & building maintainable software that directly interfaces with test hardware and equipment. This isn't high-level applicatio
Full-time
San Jose, California
•
Today
Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Broadcom's ASIC Product Division is seeking candidates for a DFT position at our San Jose, California, Development Center. The candidate would be required to work on various phases of SoC DFT related activities for Broadcom APD (ASIC Products Division)
Full-time
USD 81,000.00 - 130,000.00 per year
Santa Clara, California
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Today
About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleetin
Full-time
USD 128,000.00 - 189,370.00 per year
San Jose, California
•
Today
Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Broadcom's ASIC Product Division (APD) is seeking candidates for a DFT position at our San Jose, California, Development Center. The successful candidate will be responsible for leading DFT programs all the way from chip level DFT specification, throug
Full-time
USD 141,300.00 - 226,000.00 per year
Saratoga, California
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Today
Ready to make connectivity from space universally accessible, secure and actionable? Then you've come to the right place! E-Space is bridging Earth and space to enable hyper-scaled deployments of Internet of Things (IoT) solutions and services. We are building a highly-advanced low Earth orbit (LEO) space system that will fundamentally change the design, economics, manufacturing and service delivery associated with traditional satellite and terrestrial IoT systems. We're intentional, we're una
Full-time
USD 120,000.00 - 220,000.00 per year
Saratoga, California
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4d ago
We re looking for a seasoned DFT Leader to architect and drive test strategy for complex multi-chip SoCs at advanced nodes (7nm and below). Own DFT architecture (Scan, LBIST, MBIST, Memory Repair, OCC, ACJTAG/DCJTAG) Lead ATPG & achieve high @speed scan coverage Hands-on with Synopsys or Mentor test tools Multiple deep submicron tape-outs required SerDes + EMIB exposure is a plus 15+ years semiconductor experience This is a high-impact leadership role shaping next-gen high-performance silicon.
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Full-time
Depends on Experience
Santa Clara, California
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7d ago
Key Responsibilities Architect, implement, and validateDFT solutionsto improve controllability and observability in complex GPU/SoC designsLeadscan-based DFT implementation, including scan insertion, compression, and test logic integrationDevelop and debugATPG patternstargeting stuckat, transition, and additional fault modelsImplement and supportMBIST architecturesfor onchip memory test, diagnosis, and coverage improvementPerformIO Test planning and validationto ensure reliable interface and pin
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Contract, Third Party
Depends on Experience
Santa Clara, California
•
Today
Company:Qualcomm Technologies, Inc. Job Area:Engineering Group, Engineering Group > CPU Engineering General Summary: As a DFT Engineer you will work with chip architects, chip designers, implementation engineers and test engineers to verify the DFT and DFD (Design for Debug) architecture, implementation, and test plans for both mixed signal and digital VLSI designs. Then you?ll insure it becomes reality. We?re doing a ground up implementation of a new chip architecture, so you?ll have to ability
Full-time
Compensation information provided in the description
Remote
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26d ago
12+ month contractRemote/3 Main priorities below: 1- Tile Based Approach 2-Tessent SSN- specifically SSN 3- MCM Packages/Die-To-Die Chips DFT engineer- Expert with Tessent tools. Experience with Tessent SSN. Experience working on ATPG, MBIST, JTAG, DFT Insertion. Experience with own DFT Verification. Experience with ICL PDL.
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Contract
60 - 90
Remote or Austin, Texas
•
Today
For over four decades, Cirrus Logic has been propelled by the top engineers in mixed-signal processing. Our rockstar team thrives on solving complex challenges with innovative end-user solutions for the world's top consumer brands. Cirrus Logic is also known for its award-winning culture, which was built on a foundation of inclusion and fairness, meaningful community engagement, and delivering enjoyable employee experiences at every turn. But we couldn't do it without our extraordinary workforce
Full-time
Remote
•
Today
K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by $450M from leading investors including Altimeter Capital, Redpoint Ventures, T. Rowe Price, Lightspeed Venture Partners, Alpine Space Ventures, and others - with an additional $500M in signed contracts across commercial and US government customers - we're mass-producing the highest-power satellite platforms ever built for missions from LEO to deep
Full-time
USD 170,000.00 - 250,000.00 per year
Santa Clara, California
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11d ago
Strong understanding of: DFT concepts (Scan, ATPG, MBIST, JTAG) Digital design fundamentals Hands-on experience with: SystemVerilog and UVM Simulation tools such as VCS, Xcelium, or Questa Preferred Skills Familiarity with: ATPG tools (TetraMAX, Modus, FastScan) Debug tools (Verdi, DVE) Understanding of: Low-power design methodologies (UPF/CPF) Clocking and reset architectures
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Contract
50 - 60
