DFT jobs in Mountain View, CA

Santa Clara, California

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Today

Job Description: 5+ years of hands-on experience in DFT and ATPG for SoC or ASIC designs Strong understanding of DFT fundamentals including controllability, observability, and scan-based testing Proven expertise in ATPG pattern generation, analysis, and debug Experience with MBIST, including memory test architectures and diagnostics Knowledge of IO Test methodologies for interface and pin level validation Solid understanding of clock DFT and clock verification concepts Strong grasp of digital de

Full-time

USD130000.0/ANNUAL - USD150000.0/ANNUAL

Design For Test (DFT) Engineer

San Jose, California

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Today

Job Description Onsite San Jose - 5 days a week Description The team is looking for a Design-for-Test contractor to test and validate the next generation Samsung chips. Candidate will be responsible to work with Front End and Physical Design teams to implement DFT and test designs which will impact the product lines for radio frequency (RF) and BlueTooth/Wireless LAN chipsets. JOB RESPONSIBILITIES: Experience with memory BIST - Siemens Tessent Flow Experience with gate-level simulation and si

Contract

DFX/DFT Engineer

Santa Clara, California

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Today

DFX/DFT Engineer Location : Bay area CA Experience :- 6 to 8 yrs Onsite 6-12 months JD:- We are looking for a highly motivated DFX Engineer to develop, implement, verify, and validate advanced Design-for-Test (DFT/DFX) solutions for complex SoCs and ASICs. The candidate will work closely with Architecture, Design, Verification, Physical Design, and Post-Silicon teams to ensure robust manufacturability, testability, and silicon quality. Key Responsibilities Create and execute test plans for DF

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Contract

Depends on Experience

DFT Engineers

Santa Clara, California

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28d ago

5+ years of hands-on experience in DFT and ATPG for SoC or ASIC designsStrong understanding of DFT fundamentals including controllability, observability, and scan-based testingProven expertise in ATPG pattern generation, analysis, and debugExperience with MBIST, including memory test architectures and diagnosticsKnowledge of IO Test methodologies for interface and pin level validationSolid understanding of clock DFT and clock verification conceptsStrong grasp of digital design and RTL fundamenta

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Contract

Depends on Experience

DFT Engineer

Santa Clara, California

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21d ago

Job title: DFT Engineer Location: Santa Clara, California 5+ years of hands-on experience in DFT and ATPG for SoC or ASIC designs Strong understanding of DFT fundamentals including controllability, observability, and scan-based testing Proven expertise in ATPG pattern generation, analysis, and debug Experience with MBIST, including memory test architectures and diagnostics Knowledge of IO Test methodologies for interface and pin level validation Solid understanding of clock DFT and clock ve

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Contract

DFT Engineer in San Jose, CA (Hybrid role)

Hybrid in San Jose, California

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Yesterday

Role: DFT Engineer Location: San Jose, CA (Hybrid role) Duration: 12+ months Job description: Good understanding of DFT fundamentals and methodologyExperience with DFT insertion and verificationExperience with Tessent tools:Tessent Streaming Scan Network Op SWTessent Memory BIST-NS Ap SWTessent Memory BIST-NS repair Op SWTessent Test Kompress Ap SWTessent IJTAG Ap SWTessent Scan Pro Ap SWAbility to work under pressure and debug issues promptly

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Contract, Third Party

Depends on Experience

Design For Test (DFT) Engineer

San Jose, California

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Yesterday

Role: Design For Test (DFT) Engineer Location: San Jose, CA (Onsite: M-F) Duration: 6 Months Contract Pay Rate: $100-130/hr W2 Description: Looking for a Design-for-Test contractor to test and validate the next generation chips. Candidate will be responsible to work with Front End and Physical Design teams to implement DFT and test designs which will impact the product lines for radio frequency (RF) and BlueTooth/Wireless LAN chipsets. Job Responsibilities: Experience with memory BIST Siemens

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Contract

100 - 130

DFT Engineer

San Jose, California

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29d ago

DFT EngineerIntroduction:The DFT Engineer position at Sivaltech Inc involves working on ASIC/SoC designs, implementing Design for Testability (DFT) techniques, and ensuring the efficient testing of semiconductor devices. The role requires expertise in DFT tools, verification, testing, and debugging to support the overall product development lifecycle. Responsibilities:Implement DFT strategies for ASIC/SoC designsWork on Scan, JTAG, BIST, and MBIST techniquesGenerate test patterns and verify DFT

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Contract, Third Party

Depends on Experience

CPU Core Staff DFT Engineer

Santa Clara, California

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Today

ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world's most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you're designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger - technology that moves the world forward. Joi

Full-time

USD 175,000.00 per year

DFT Engineer

San Jose, California

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Today

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Broadcom's Core Switching Group division is seeking a candidate for a DFT engineer. Products include networking switches for Scale up and Scale Out for traditional and AI data centers. This position is at our R&D center in San Jose, CA. The successful

Full-time

USD 121,900.00 - 195,000.00 per year

DFT Engineers - Santa Clara, CA

Santa Clara, California

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30+d ago

Job Title: DFT Engineers Location: Santa Clara, CA Job Description: 5+ years of hands-on experience in DFT and ATPG for SoC or ASIC designsStrong understanding of DFT fundamentals including controllability, observability, and scan-based testingProven expertise in ATPG pattern generation, analysis, and debugExperience with MBIST, including memory test architectures and diagnosticsKnowledge of IO Test methodologies for interface and pin level validationSolid understanding of clock DFT and clock ve

Easy Apply

Contract

Depends on Experience

Engineering Intern - ASIC DFT (Spring 2027 Co-Op)

Palo Alto, California

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Today

About Rivian Rivian is on a mission to keep the world adventurous forever. This goes for the emissions-free Electric Adventure Vehicles we build, and the curious, courageous souls we seek to attract. As a company, we constantly challenge what's possible, never simply accepting what has always been done. We reframe old problems, seek new solutions and operate comfortably in areas that are unknown. Our backgrounds are diverse, but our team shares a love of the outdoors and a desire to protect it

Full-time

USD 45.00 - 51.00 per hour

ASIC DFT Engineer

Palo Alto, California

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Today

Full-time

Compensation information provided in the description

DFT (Design for Test) Engineer (California, Texas) - W2 Only

San Jose, California

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Yesterday

Hello, Hope you are doing good ! Please find the JD below and share your updated resume POSITION: DFT (Design For Test) Engineer Location: San Jose, CA and Austin, TX Requirements: Good understanding of DFT fundamentals and methodology Experience with DFT insertion and verification Experience with Tessent tools Tessent Streaming Scan Network Op SW Tessent MemoryBIST-NS Ap SW Tessent MemoryBIST-NS repair Op SW Tessent TestKompress Ap SW Tessent IJTAG Ap SW Tessent ScanPro Ap SW Ability to work

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Full-time

$60 - $70

AI / ML DFT Project Lead

Santa Clara, California

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Today

Full-time

USD 203,000.00 per year

CPU DFT Engineer

Santa Clara, California

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Today

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > CPU Engineering General Summary: As a DFT Engineer you will work with chip architects, chip designers, implementation engineers and test engineers to verify the DFT and DFD (Design for Debug) architecture, implementation, and test plans for both mixed signal and digital VLSI designs. Then you'll insure it becomes reality. We're doing a ground up implementation of a new chip architecture, so you'll have to

Full-time

USD 142,200.00 - 213,400.00 per year

DFT Lead Engineer

San Jose, California

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Today

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Principal DFT Engineer Broadcom's ASIC Product Division is seeking candidates for a DFT position at our San Jose, California, Development Center. The successful candidate will be responsible for leading DFT programs all the way from chip level DFT spe

Full-time

USD 143,800.00 - 230,000.00 per year

DFT Engineer

Santa Clara, California

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Today

We are looking for a highly motivated DFX Engineer to develop, implement, verify, and validate advanced Design-for-Test (DFT/DFX) solutions for complex SoCs and ASICs. The candidate will work closely with Architecture, Design, Verification, Physical Design, and Post-Silicon teams to ensure robust manufacturability, testability, and silicon quality. Key Responsibilities Create and execute test plans for DFX features including Scan, MBIST, SSN, EDT, IJTAG, and JTAG. Verify DFX implementations at I

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Contract

Depends on Experience

ASIC/SOC DFT Engineer (Silicon Engineering)

Palo Alto, California

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Today

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. ASIC/SOC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world's

Full-time

USD 135,000.00 - 175,000.00 per year

Lead ASIC DFT Staff Engineer

Remote

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8d ago

Required Skills & Qualifications: Strong hands-on experience in ASIC DFT with end-to-end ownership.Solid understanding of DFT fundamentals, fault models, test techniques, and test coverage concepts.Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug.Hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools.Proven experience in scan insertion, ATPG setup, simulation, debug, and DRC analysis.Experience with MBIST implementation and verific

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Third Party, Contract

90 - 100

DFT jobs in Mountain View, CA, USA