Product Verification & Validation Engineer BCforward is currently seeking a highly motivated Product Verification & Validation Engineer for an opportunity in Fuquay-Varina NC. Position Title: Product Verification & Validation Engineer Location: Fuquay-Varina NC Anticipated Start Date: Tentative 11/20/2023. Please note this is the target date and is subject to change. BCforward will send official notice ahead of a confirmed start date. Expected Duration: 12 Months Contract Job Type: Full Ti
Description: A Product Verification & Validation Engineer ensures that prototype components and machines meet durability and performance requirements at key stages of the Product Development Process. Duties: Decides upon appropriate tests to ensure durability and performance of new designs, developing new tests when necessary. Executes test plan by conducting simple tests and assigning in-depth work to mechanics, lab engineers, field test sites, and structural analysts. Leads the team through r
Title: Lead Digital Design Verification Engineer - UVM Location: Cambridge MA (remote is available) Duration: 12 months with likely extensions Clearance: Active Secret is preferred Main requirement: Ability to create a UVM testbench from scratch. Overview: The Digital Design Team is seeking a motivated and experienced Senior Verification Engineer to tackle novel verification challenges in FPGAs and ASICs. In this role, you will apply modern verification strategies to complex digital and mixed-
12 months contract Location : Fuquay-Varina NC Visa sponsorship is not available, now or in the near future, for this position. Description: A Product Verification & Validation Engineer ensures that prototype components and machines meet durability and performance requirements at key stages of the Product Development Process. Duties: Decides upon appropriate tests to ensure durability and performance of new designs, developing new tests when necessary. Executes test plan by conducting simple t
As a member of our System IP team you will contribute to the functional verification of System IP including coherent interconnect, and executing Test plan. Work with DV team and designers to build verification environments. Develop UVM sequences, tests, scoreboards, monitors and checkers. Write SVA assertions. Functional and Code coverage Closure. Regression triaging and debug. Key Responsibilities Include: Define/plan/implement/execute functional verification strategy of complex System IP desi
Location: Cambridge, MA Salary: Depends on Experience Description: One of our clients in the Cambridge, MA area is looking to hire a Sr. Digital Design Verification Engineer for a hybrid work schedule (2-3 days onsite). This would be a direct hire role. The Digital Design Team is seeking a motivated and experienced Senior Verification Engineer to tackle novel verification challenges in FPGAs and ASICs. In this role, you will apply modern verification strategies to complex digital and mixed-s
Job Description Learn from and adhere to internal quality manual (Quality System Procedures, Work Instructions, Forms). Interact with cross-functional project teams to provide inputs to project plans and schedules. Estimate resource needs for project support. Review requirements and scrutinize for testability. Develop V&V test plans, test procedures, requirements trace matrices, and test reports. Assign project tasks and responsibilities to V&V team. Act as advisor to team to meet schedul
Mastech Digital provides digital and mainstream technology staff as well as Digital Transformation Services for all American Corporations. We are currently seeking a Silicon Design Verification Engineer for our client in the IT Services domain. We value our professionals, providing comprehensive benefits and the opportunity for growth. This is a Contract position, and the client is looking for someone to start immediately. Duration: 12 Months Contract Location: Philadelphia, PA (Hybrid) Role: Si
Job Title - ASIC Verification Engineer Location - Pleasanton CA Length - Contract (12 Months+) Technical Experience: 10+ years of ASIC verification experience with Strong experience in System Verilog testbench development and UVM methodology is a must Must have hands-on experience with at least 2 SoC/Sub-System/IP verification projects, along with SV-UVM based testbench development for at least 3 year Hands-on experience on CPU(s) based SoC verification and writing/maintaining C-SV tests Han
Requisition Number: 16806 Required Travel: 0 - 10% Employment Type: Full Time/Salaried/Exempt Security Clearance: Ability to Obtain Level of Experience: Senior This opportunity resides with Cyber & Electronic Warfare, a business group within HII's Mission Technologies division. HII works within our nation's intelligence and cyber operations communities to defend our interests in cyberspace. Our deep expertise in network architecture, software and hardware development, cybersecurity and the elec
Duration: 12 months Location: Redmond, WA (Onsite role) Job Title: Senior Design Verification Engineer Technical Experience: 10+ years of ASIC verification experience with Strong experience in System Verilog testbench development and UVM methodology is a must Must have hands-on experience with at least 2 SoC/Sub-System/IP verification projects, along with SV-UVM based testbench development for at least 3 year Hands-on experience on CPU(s) based SoC verification and writing/maintaining C-SV tests
Requisition Number: 16803 Required Travel: 0 - 10% Employment Type: Full Time/Salaried/Exempt Security Clearance: Ability to Obtain Level of Experience: Mid This opportunity resides with Cyber & Electronic Warfare, a business group within HII's Mission Technologies division. HII works within our nation's intelligence and cyber operations communities to defend our interests in cyberspace. Our deep expertise in network architecture, software and hardware development, cybersecurity and the electro
Job Title: Senior Design Verification Engineer Location: Redmond, WA USA Length - Contract (12 Months+) Experience level: 8 + Years Must have Skills: Technical Experience: 10+ years of ASIC verification experience with Strong experience in System Verilog testbench development and UVM methodology is a must Must have hands-on experience with at least 2 SoC/Sub-System/IP verification projects, along with SV-UVM based testbench development for at least 3 year Hands-on experience on CPU(s) based
Job Title : Design Verification Engineer Work Location: Redmond, WA Position Type: Contract Job Description: Technical Experience: 10+ years of ASIC verification experience with Strong experience in System Verilog testbench development and UVM methodology is a must. Must have hands-on experience with at least 2 SoC/Sub-System/IP verification projects, along with SV-UVM based testbench development for at least 3 years. Hands-on experience on CPU(s) based SoC verification and writing/maintaining C
Drapers Digital Design Team is seeking a motivated and experienced Senior Verification Engineer to tackle novel verification challenges in FPGAs and ASICs. In this role, you will apply modern verification strategies to complex digital and mixed-signal designs in the areas of embedded security, cryptography, signal and image processing, navigation and communications. You will develop verification approaches, author and execute verification plans, and use formal analysis tools. You will work in m
Title: Silicon Design Verification Engineer Location: Philadelphia, PA(Hybrid) Duration: 12-months to begin with Electrical Engineering - Design Integrated Circuits (IC) that power everyday electronic devices. Design custom or semi-custom silicon used on electronic devices, cloud infrastructure, machine learning, and AI computational platforms. Work across the entire silicon design lifecycle, including system architecture, design verification, RTL digital design, physical design, design for test
Akkodis is seeking a skilled Silicon Design Verification Engineer to work on-site with our client in Philadelphia, PA. As the successful candidate, you will be responsible for developing formal test plans, executing complete formal verification sign-off of single or multiple complex blocks, and partnering with cross-functional teams towards creating a first-pass silicon success. This is an excellent opportunity to grow your career while working on exciting projects with a dynamic team! Responsi
Please contact Abdul on "" OR email me at "" Technical Experience: 10+ years of ASIC verification experience withStrong experience in System Verilog testbench development and UVM methodology is a mustMust have hands-on experience with at least 2 SoC/Sub-System/IP verification projects, along with SV-UVM based testbench development for at least 3 yearHands-on experience on CPU(s) based SoC verification and writing/maintaining C-SV testsHands-on experience with UVM and System Verilog through devel
Title: Sr. Software Verification Engineer DO-178C Location: Camarillo, CA 100% On-site Locals Highly Preferred Length of Contract: 6-9 months+ Hours per week: 40 (8-hour days) US Ctiizen or /Perm Res Need to be able to work on ITAR products. Background Check/Drug Screen Required Ideal Start Date: Mid-to-Late January but can identify someone now to start in beginning of December 23 for 2 weeks before the dead week. Scope of work: Currently there are 3 projects going through verification pha
Role: Silicon Design Verification Engineer Duration:0-12 month(s) Remote: Hybrid Local: Yes VISA: with Security clearance possibly Education: Bachelor's Degree MUST HAVE: 1. UVM 2. System VerilogElectrical Engineering - Design Integrated Circuits (IC) that power everyday electronic devices. Design custom or semi-custom silicon used on electronic devices, cloud infrastructure, machine learning, and AI computational platforms. Work across the entire silicon design lifecycle, including system archi
