Perl jobs | Dice.com

Hybrid in Livermore, California

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Today

Job Title: Senior Software Engineer Python/Perl, Django & Oracle Job Description: We are seeking a Senior Software Engineer to support and maintain the Environmental Information Management System (TEIMS) application suite used by Environmental, Safety and Health (ESH) and Environmental Restoration Department (ERD) teams. This role focuses on troubleshooting, break/fix support, bug fixes, and ongoing maintenance of existing web applications. The engineer will work with business stakeholders and t

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Contract, Third Party

Depends on Experience

Design Verification Engineer

San Jose, California

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3d ago

Job Description: We are seeking Design Verification Engineer with exposure on Developing and maintaining UVM/SystemVerilog testbenches for high-performance IPs (compute arrays, DMAs, NoCs, memory subsystems). What You'll Be Doing: Strong in SV/UVM scale test bench AXI expertise, NOC/Crossbar, Performance Regression/Triage and coverage closure Need asap Program has already started and is in execution Ability to work on Amazon tools, flows, methodology. Work is in start-up mode with less docume

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Contract, Third Party

60 - 70

DFT Engineer

California

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Today

Job Title: DFT Engineer Location: Saratoga, CA (Onsite) Duration: Contract & Full-Time Job Description: Define the DFT architecture of a multi-chip system SOC. involving all aspects of test design functions such as Scan, BIST, Memory Repair, BSD ( ACJTAG/DCJTAG). Proficiency in Synthesis design constraints. ( Ie SDC) Prior experience with Serializers/Deserilizers. Sound Proficiency in either Mentor /Synopsys Test Tools required. Proficiency is synthesis, Define and implement OCC. Exposure to

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Full-time

DV Engineer - San Jose, CA / Austin, TX

Hybrid in San Jose, California

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Today

DTS is looking for DV Engineer for our direct client position in San Jose, CA / Austin, TX Role description: Responsibilities: Develop and implement comprehensive functional verification environments, including monitors, checkers, scoreboards, and assertionsUtilize expertise in AMBA bus protocols, ARM CPU, and optionally PCI Express and/or Ethernet bus protocols to ensure robust verification processesCollaborate with cross-functional teams to integrate and troubleshoot verification components w

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Contract, Third Party

Depends on Experience

Web Developer / Engineer

Battle Creek, Michigan

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Today

TECHNOGEN, Inc. is a Proven Leader in providing full IT Services, Software Development and Solutions for 15 years. TECHNOGEN is a Small & Woman Owned Minority Business with GSA Advantage Certification. We have offices in VA; MD & Offshore development centers in India. We have successfully executed 100+ projects for clients ranging from small business and non-profits to Fortune 50 companies and federal, state and local agencies. Position: Web Developer / Engineer Location: Battle Creek, MI( Onsi

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Contract

$DOE

RTL/STA Engineer

San Jose, California

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Today

Position: Senior RTL / STA Engineer Location: San Jose, California (on-site preferred), USA Role Overview Ciscos ASIC Engineering group is seeking a senior RTL / Static Timing Analysis (STA) contractor to support timing constraint development and verification, RTL design, and timing closure across ASIC design flows. The preferred work location is Ciscos San Jose campus. Candidates with at least 8 years of relevant experience are preferred; candidates with somewhat less experience may be consider

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Full-time, Third Party

0 - 0

DFT MBIST Staff Engineer

Remote

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Today

Position: DFT MBIST Staff Engineer Position Summary: We are looking for a highly experienced Senior MBIST Contractor to join our SoC Design-for-Test (DFT) team. The role is focused on hands-on Memory BIST implementation using Synopsys MBIST (SMS). The ideal candidate is an independent contributor who can own the complete MBIST flow from insertion through verification, simulation, pattern generation, and Silicon bring-up with minimal supervision. Responsibilities: Perform MBIST insertion for c

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Full-time, Third Party

0 - 0

DFT MBIST Staff Engineer

Remote

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Today

Position Summary: We are looking for a highly experienced Senior MBIST Contractor to join our SoC Design-for-Test (DFT) team. The role is focused on hands-on Memory BIST implementation using Synopsys MBIST (SMS). The ideal candidate is an independent contributor who can own the complete MBIST flow from insertion through verification, simulation, pattern generation, and Silicon bring-up with minimal supervision. Responsibilities: Perform MBIST insertion for complex SoC designs using Synopsys SMS

Contract

USD70.0/HOURLY - USD80.0/HOURLY

Verification Engineer

Sunset Valley, Texas

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20d ago

Job Description: Hands-on experience with VC Formal (Synopsys) and/or Jasper Gold (Cadence) Strong proficiency in System Verilog Assertions (SVA) and formal property specification Experience with formal verification applications: FPV, connectivity checking, register verification, equivalence checking, and coverage analysis Familiarity with scripting languages (TCL, Python, Perl) for flow automation Extensive experience in design verification with a strong focus on formal verification Expertise i

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Contract, Third Party

Depends on Experience

DV Engineer

Hybrid in Austin, Texas

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Today

Title: DV EngineerLocation: Austin, TX and San Jose, CA(Hybrid)Duration: 6+ Months Responsibilities Develop and implement comprehensive functional verification environments,including monitors, checkers, scoreboards, and assertionsUtilize expertise in AMBA bus protocols, ARM CPU, and optionally PCI Expressand/or Ethernet bus protocols to ensure robust verification processesCollaborate with cross-functional teams to integrate and troubleshoot verificationcomponents within the overall systemEmplo

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Third Party, Contract

Depends on Experience

DFT (Design for Test) Engineer_SanJose, CA (Onsite)

San Jose, California

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Today

Design for Test (DFT) Engineer Location: San Jose, CA Duration: 12 + Months (Potential Extension) Interview Process: Virtual/Onsite Rate: Up to $130/hr on W2 (No Benefits) Job OverviewWe are seeking an experienced Design for Test (DFT) Engineer to support the development and validation of next-generation semiconductor products. The role involves close collaboration with Front-End Design and Physical Design teams to implement and optimize DFT solutions for advanced wireless and connectivity c

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Contract

100 - 130

Senior Software Engineer

Livermore, California

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7d ago

Job Description We have an opening for aSenior Software Engineersupporting the Environmental Information Management System (TEIMS) application suite used by the Environment, Safety and Health (ESH) Directorate and the Environmental Restoration Department (ERD). As a senior software engineer, you will play a vital role in keeping LLNL employees and our environment safe. You will be responsible for performing break/fix support of applications within TEIMS used to support operations and environment

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Contract

Depends on Experience

Data Migration Lead

Santa Clara, California

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Today

Job title: Data Migration Lead Location: Santa Clara Valley, CA ( Onsite from Day 1 ) Project Type: Long term contract Data Migration Lead onsite: 12+ years of Teamcenter PLM experience with 5+ years in Data Migration.Strong hands-on experience in PLMXML, TcXML, csv2tcxml, IPS Uploads, and Teamcenter import/export utilities.Experience in large-volume data migration from legacy systems to Teamcenter.Good functional and technical knowledge of Teamcenter Data Model, BMIDE, Item Types, and migratio

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Contract, Third Party

Depends on Experience

Senior F5 Load Balancer Engineer

Hybrid in Charlotte, North Carolina

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Today

Job Title: Senior F5 Load Balancer Engineer - W2 position Job Location: Chandler, AZ / Charlotte, NC / Plano, TX (3 Days Onsite, 2 Days Remote) hybrid role. Job Type: 18+ Months ContractJob Descriptions: We are seeking a Senior F5 Load Balancer Engineer to support complex, large-scale initiatives within a financial services environment. This role requires strong expertise in F5 Networks and VMware AVI, along with a solid background in enterprise networking, application infrastructure, and securi

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Contract

50 - 60

Verification Engineer

Austin, Texas

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Today

Job Description Description: Hands-on experience with VC Formal (Synopsys) and/or Jasper Gold (Cadence) Strong proficiency in System Verilog Assertions (SVA) and formal property specification Experience with formal verification applications: FPV, connectivity checking, register verification, equivalence checking, and coverage analysis Familiarity with scripting languages (TCL, Python, Perl) for flow automation Extensive experience in design verification with a strong focus on formal verificatio

Full-time

Senior Firmware Developer

Denver, Colorado

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7d ago

Role:Senior Firmware Developer Location:Denver, CO (4 days onsite/week) Interview: Video Must have skills: C++ (11/14/17) Python Perl Embedded Linux (Yocto/Buildroot) RTOS (FreeRTOS, ThreadX, Zephyr) I2C, SPI, UART, CAN, USB, TCP/IP Experienced Engineer specializing in developing, integrating, testing, and maintaining broadband, video, and IoT solutions on RDK-based devices such as set-top boxes, gateways, and routers Good to have skills: Wireless stacks (BLE, WiFi, Thread, Zigbee) Edg

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Contract

50 - 60

Product Engineer II, Conformal

San Jose, California

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Today

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. This opportunity is for a Product Engineer working with the Conformal Products. You will be part of a highly efficient and independently-minded team of engineering professionals focused on our top customer's success. You will also be working closely with R&D to help deliver new product features, enhancements, and solutions. Must be able to work with strict deadlines, provide systematic

Full-time

USD 105,000.00 - 195,000.00 per year

Orchestrator - Senior Engineer

Remote

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3d ago

Job Description: Experience in backend cloud infrastructure development.Language Proficiency: Strong proficiency in Perl (legacy services), along with Go and Python.System Programming: Deep understanding of Linux OS internals, process management, memory optimization, and RESTful APIs.Hardware Awareness: Knowledge of ARM64 architecture, CPU affinity, and NUMA memory allocation.Virtualization: Experience working with VM lifecycle management and orchestration APIs. Job Responsibilities: Refactor an

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Third Party, Contract

Depends on Experience

CPU Low Power RTL Design Engineer

Santa Clara, California

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Today

Company:Qualcomm Technologies, Inc. Job Area:Engineering Group, Engineering Group > CPU Engineering General Summary: We are hiring talented engineers for CPU RTL development targeted for high performance, low power devices. In this role, you will work with chip architects to conceive of the micro-architecture and help with architecture/product definition through early involvement in the product life cycle. Required for this Role: MS degree in Computer or Electrical Engineering or BS degree in C

Full-time

Compensation information provided in the description

Linux Admin + VCS

Irving, Texas

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Today

Experience:Strong experience with Linux fundamentals and VCSis mandatory Job Details: Responsible for OS Upgrades - complex environment Both VM and Physical and various firmware upgrade procedures. Should have knowledge about OS Compliance tools and its setup.Must be able to configure & troubleshoot HBA and NIC load balancing.OS installation and configurationUNIX shell scripting & Perl scripting knowledgeShould have exposure on RAC cluster pre-requisite setup.Should have knowledge on VCS cluster

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Full-time

Depends on Experience